CCS/TMS320F280049: Phase Shift Problem

I have already configured like this:

configHRPWM( 4, period200k, 1);

configHRPWM( 7, period200k, 3);

void configHRPWM(uint16_t j, uint16_t period, int16 mode)
{
(*ePWM[j]).TBCTL.bit.PRDLD = TB_SHADOW; // set Immediate load
(*ePWM[j]).TBPRD = period-1; // PWM frequency = 1 / period
(*ePWM[j]).CMPA.bit.CMPA = period * 0.2; // set duty 20% initially
(*ePWM[j]).CMPA.bit.CMPAHR = (1 << 8); // initialize HRPWM extension
(*ePWM[j]).CMPB.bit.CMPB = period * 0.8; // set duty 80% initially
(*ePWM[j]).CMPB.all |= (1 << 8); // initialize HRPWM extension
(*ePWM[j]).TBPHS.all = 0;
(*ePWM[j]).TBCTR = 0;

(*ePWM[j]).TBCTL.bit.CTRMODE = TB_COUNT_UP;
if (mode == 1) { // config as a Master
(*ePWM[j]).TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
(*ePWM[j]).TBCTL.bit.PHSEN = TB_DISABLE;//TB_DISABLE;
}
if (mode == 2) { // config as a Slave (Note: Phase+2 value used to compensate for logic delay)
(*ePWM[j]).TBPHS.bit.TBPHS = 2; //phase delay
(*ePWM[j]).TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
(*ePWM[j]).TBCTL.bit.PHSEN = TB_ENABLE;
}
if (mode == 3) { // config as a Slave (Note: Phase+2 value used to compensate for logic delay)
(*ePWM[j]).TBPHS.bit.TBPHS = 2 + period*0.5; //phase delay
(*ePWM[j]).TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
(*ePWM[j]).TBCTL.bit.PHSEN = TB_ENABLE;
}
(*ePWM[j]).TBCTL.bit.HSPCLKDIV = TB_DIV1;
(*ePWM[j]).TBCTL.bit.CLKDIV = TB_DIV1;
(*ePWM[j]).TBCTL.bit.FREE_SOFT = 11;

(*ePWM[j]).CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
(*ePWM[j]).CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
(*ePWM[j]).CMPCTL.bit.SHDWAMODE = CC_SHADOW;
(*ePWM[j]).CMPCTL.bit.SHDWBMODE = CC_SHADOW;

(*ePWM[j]).AQCTLA.bit.ZRO = AQ_SET; // PWM toggle high/low
(*ePWM[j]).AQCTLA.bit.CAU = AQ_CLEAR;
(*ePWM[j]).AQCTLB.bit.CAU = AQ_SET;
(*ePWM[j]).AQCTLB.bit.ZRO = AQ_CLEAR;

EALLOW;
(*ePWM[j]).HRCNFG.all = 0x0;
(*ePWM[j]).HRCNFG.bit.EDGMODE = HR_BEP; // MEP control on both edge
(*ePWM[j]).HRCNFG.bit.CTLMODE = HR_CMP;
(*ePWM[j]).HRCNFG.bit.HRLOAD = HR_CTR_ZERO_PRD;
(*ePWM[j]).HRCNFG.bit.EDGMODEB = HR_BEP; // MEP control on falling edge
(*ePWM[j]).HRCNFG.bit.CTLMODEB = HR_CMP;
(*ePWM[j]).HRCNFG.bit.HRLOADB = HR_CTR_ZERO_PRD;
// #if (AUTOCONVERT)
(*ePWM[j]).HRCNFG.bit.AUTOCONV = 1; // Enable auto-conversion
// logic
// #endif
(*ePWM[j]).HRPCTL.bit.HRPE = 1; // Turn off high-resolution period
// control.
(*ePWM[j]).HRPCTL.bit.TBPHSHRLOADE = 1; // enable TBPHSHR sync
(*ePWM[j]).HRMSTEP.all = MEP_ScaleFactor;
EDIS;

(*ePWM[j]).DBCTL.bit.IN_MODE = DBA_ALL; //EPWM7A is the source for both falling-edge and rising-edge delay
(*ePWM[j]).DBRED.bit.DBRED = 5; //Rising Edge Delay Count. 100n/10n
(*ePWM[j]).DBFED.bit.DBFED = 5; //Falling Edge Delay Count. 100n/10n
(*ePWM[j]).DBCTL.bit.POLSEL = 0x02; //EPWM7B is inverted
(*ePWM[j]).DBCTL.bit.OUT_MODE = 0x3; //Both EPWM7A EPWM7B has deadband function

EALLOW;
(*ePWM[j]).TZCTL.bit.TZA = 2;
(*ePWM[j]).TZCTL.bit.TZB = 2;
(*ePWM[j]).TZFRC.bit.OST = 1;
EDIS;
}