TMS320F28377D: Power up sequence

Ryo Akashi

Genius 9470 points

Part Number: TMS320F28377D

Hello experts,

I got question about power-up sequence from customer.

From datasheet, there are some requirement in below;

1.) The 3.3-V supplies should be powered up together and kept within 0.3 V of each other during functional operation.

2.) During the ramp, VDD should be kept no more than 0.3 V above VDDIO.

3.) The supplies should ramp to full rail within 10 ms and supply ramp rate should be larger than 330V/s.

The sequence limitation between VDD(1.2V) ramp and VDDIO(3.3V) ramp is only 2.). Is it correct?

For example, is it no problem to take some time (100ms ~ few seconds) between 3.3V ramp and 1.2V ramp?

I would appreciate if you would give me advice.

Thanks and best regards,

Ryo Akashi

over 5 years ago

0 Nirav Ginwala over 5 years ago

TI__Genius 15385 points

Hi Akashi,

Let me check with experts and I will try to get back with you early next week.

Regards,

Nirav

0 Nirav Ginwala over 5 years ago in reply to Nirav Ginwala

TI__Genius 15385 points

Hi Akashi,

I am not sure if you are referring to the latest Data Manual for TMS320F2837D, but if you look into section "5.9.1.3 VDD Requirements" it says "VDD should be kept no more than 0.3 V above VDDIO".

Regards,

Nirav

0 Ryo Akashi over 5 years ago in reply to Nirav Ginwala

TI__Genius 9470 points

Hello Nirav-san,

Thank you for your reply.

Yes, I understand we should follow "VDD should be kept no more than 0.3V above VDDIO".

My question is that it is no problem to take some time (100ms ~ few seconds) between 3.3V ramp and 1.2V ramp or not.

In "5.9.1.4 Supply Ramp Rate", there is description about each ramp time, but there is no description about interval of VDD ramp and VDDIO ramp.

Could you give me advice about this point?

Thanks and best regards,

Ryo Akashi

0 Nirav Ginwala over 5 years ago in reply to Ryo Akashi

TI__Genius 15385 points

Hi Akashi,

Please find the highlighted text in below note, regarding ramping up and down of VDD and VDDIO supply. They should ramp together.

0 Ryo Akashi over 5 years ago in reply to Nirav Ginwala

TI__Genius 9470 points

Hello Nirav-san,

Thank you for your reply.

Ok, I understand VDD and VDDIO supply should ramp together.

Is this limitation come from internal OSC frequency drift?

Even if we use external OSC, should we follow this ramp up?

I would appreciate if you would give me reply.

Thanks and best regards,

Ryo Akashi

0 Ryo Akashi over 5 years ago in reply to Ryo Akashi

TI__Genius 9470 points

Hello Nirav-san,

Could you give me comment?

Thanks and best regards,

Ryo Akashi

0 Nirav Ginwala over 5 years ago in reply to Ryo Akashi

TI__Genius 15385 points

Hi Akashi,

If customer is using external Oscillator than it is not required to ramp VDDIO and VDD together, it should be fine to ramp up VDD post VDDIO ramp up.

So, to answer your initial question:

"My question is that it is no problem to take some time (100ms ~ few seconds) between 3.3V ramp and 1.2V ramp or not."

Yes it should not be a problem to take some time (few seconds) between 3.3V ramp and 1.2V ramp.

Regards,

Nirav

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TMS320F28377D: Power up sequence