TMS320F280049: Interrupt nesting and customized priority

Brian Wang0

Part Number: TMS320F280049
Other Parts Discussed in Thread: C2000WARE, MG2

Hi team,

My customer is trying to achieve interrupt nesting and customized priority in their code. Here is some questions we got:

For this topic, we are mainly refer to TI wiki

http://processors.wiki.ti.com/index.php/Interrupt_Nesting_on_C28x

1. According to the C28x interrupt service routine table, when interrupt is served, the HW would disable the interrupt step 1~4. When is the interrupt re-enabled? Is it by S/W or H/W?

2. In the example you give, why a DINT is needed? By 'insert ISR code here', does it mean we directly insert the ISR code in the current ISR, or it is another ISR function? If we directly insert the code here, why this is a nesting?

 uint16_t TempPIEIER;
   TempPIEIER = PieCtrlRegs.PIEIER2.all; // Save PIEIER register for later
   IER |= 0x002;                         // Set global priority by adjusting IER
   IER &= 0x002;
   PieCtrlRegs.PIEIER2.all &= 0x0002;    // Set group priority by adjusting PIEIER2 to allow INT2.2 to interrupt current ISR
   PieCtrlRegs.PIEACK.all = 0xFFFF;      // Enable PIE interrupts
   asm("       NOP");                    // Wait one cycle
   EINT;                                 // Clear INTM to enable interrupts
   //
   // Insert ISR Code here.......
   // for now just insert a delay
   //
   for(i = 1; i <= 10; i++) {}/
   //
   // Restore registers saved:
   //
   DINT;
   PieCtrlRegs.PIEIER2.all = TempPIEIER;

3. When using EINT, DINT, which register are we operating? Is it INTM?

Thanks,

Brian

over 5 years ago

0 KARTHIKEYAN RAJAMANICKAM over 5 years ago

TI__Genius 11645 points

Brian,

Can you take a quick look at the below example from driverlib

..\C2000Ware_3_02_00_00\driverlib\f28004x\examples\interrupt\interrupt_ex2_sw_prioritization

0 Brian Wang0 over 5 years ago in reply to KARTHIKEYAN RAJAMANICKAM

TI__Expert 5400 points

Sure, I am aware of this example. Please also kindly help to take care of the other questions.

Regards,

Brian

0 KARTHIKEYAN RAJAMANICKAM over 5 years ago in reply to Brian Wang0

TI__Genius 11645 points

Brian,

1. According to the C28x interrupt service routine table, when interrupt is served, the HW would disable the interrupt step 1~4. When is the interrupt re-enabled? Is it by S/W or H/W?

Its done by Hardware after execution of IRET instruction (Pls refer to Step-12)

This is precisely the main body of the ISR code which can be interrupted by others. Once you are done with this ISR, then you disable interrupts(DINT) to graciously restore and exit this interrupt.

3. When using EINT, DINT, which register are we operating? Is it INTM?

Yes, EINT clears INTM bit and DINT sets INTM bit.

Hope this helps.

0 Brian Wang0 over 5 years ago in reply to KARTHIKEYAN RAJAMANICKAM

TI__Expert 5400 points

Hi Karthik,

Thanks for the reply which is pretty clear.

Another question is about interrupt_ex2_sw_prioritization priority logic:

Can you give some information about different masks(eg.MINT1 and MG1_2 )?

I can understand MINT1 is a mask that we apply to IER in a group 1 ISR, to decide which other group has higher priority than group one ,thus we could enable those.

1. What about MG1_2? Not sure what does this mean. Seems it should be the mask on interrupt level. Eg: If interrupt 2.5 has higher priority than interrupt 3.1, we not only needs to enable IER for group 2 in interrupt 3.1, we also needs to set PIEIER for interrupt 3.1, is that corrent?

2. With current logic, seems the group priority always works first than interrupt level priority. We defines group priority first and then the priority with the group. Is that the correct understanding?

Regards,

Brian

0 Brian Wang0 over 5 years ago in reply to Brian Wang0

TI__Expert 5400 points

Hi Karthik,

Any follow up here?

Regards,

Brian

0 KARTHIKEYAN RAJAMANICKAM over 5 years ago in reply to Brian Wang0

TI__Genius 11645 points

Brian,

One of our C2000ware experts will help you with the explanation on the example.

0 Vasudha Bhadoria over 5 years ago in reply to Brian Wang0

TI__Genius 10845 points

Hi Brian,

Please find below the information on different masks:

Masks for setting global priority inside ISR (to update IER register as per desired priority)
- MINT1-MINT16 (Enables higher priority interrupts in IER register)
Masks for setting group priority inside ISR(to update PIEIER as per desired group priority):
- Group 1 masks: MG1_1 – MG1_16 (Enables higher priority group interrupts in PIEIER register)
- Group 2 masks: MG2_1 – MG2_16
- -
- -
- Group 12 masks: MG12_1 – MG12_16
Masks for enabling the current interrupt inside ISR before applying group priority masks to allow same group higher priority interrupts
- M_INT1 - M_INT12

Thanks

Vasudha

0 Vasudha Bhadoria over 5 years ago in reply to Brian Wang0

TI__Genius 10845 points

Hi Brian,

Brian Wang0 said:
What about MG1_2? Not sure what does this mean. Seems it should be the mask on interrupt level. Eg: If interrupt 2.5 has higher priority than interrupt 3.1, we not only needs to enable IER for group 2 in interrupt 3.1, we also needs to set PIEIER for interrupt 3.1, is that corrent?

No, the group priority will come into picture when you need to set priority between interrupts of same group. E.g. 3.1, 3.2 and 3.3.

E.g. HWREGH(PIECTRL_BASE + PIE_O_IER1) &= MG1_7;

The above statement enables the group interrupts in PIEIER register which have higher priority than 1.7 interrupt.

Thanks
Vasudha

0 Brian Wang0 over 5 years ago in reply to Vasudha Bhadoria

TI__Expert 5400 points

Hi Vasudha,

It is pretty clear. Thanks a lot.

Regards,

Brian

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TMS320F280049: Interrupt nesting and customized priority