Part Number: TMS320F28377D
Is the delay from when the reset signal is set low to when the processor will reset defined somewhere?
I'm generating a PWM output and from measuring some signals it takes about 700ns from the XRS being set low to the PWM to stop running.
Is there a min/max/typical time for this? The only thing that I've found in the data sheets is the pulse duration (100us) and the watchdog generated XRS pulse (512 osc clock cycles).