TMS320F28379D: Unable to receive 18-Bit SPI data from ADC chip; using 9-bit SPI transfers in two chunks with FIFO, not working.

Hi all, good day.

I am using an LTC2338 18-bit ADC to sample for one of my power electronic projects. I am doing the SPI transfers using 9 bit chunks and by using the FIFO functionalities. I was successfully able to read data from a 16 bit ADC and using SPI. But when I shift to the FIFO based 18-bit ADC approch, nothing happens. The PWM interrupt that starts the SPI transmit doesent even fire; strange.

Here's my initialization code and interrupt service rountine codes for the application. I've never used FIFO type SPI befor and may have improperly configured the SPI or am using it incorrectly in the ISR. Please comment on my code.

void SPI_INIT(void)
{
    //Setup SPI to do three 9-bit FIFO transfers so that it subsequently receives 9 bits over SPI receive
    //The transmits are dummy; the receives contain the data

    SpiaRegs.SPICCR.bit.SPISWRESET = 0; //Reset the SPI peripheral
    SpiaRegs.SPICTL.bit.MASTER_SLAVE = 1; //Configure C2000 as an SPI master

    //The clock phase refers to which clock edge the data is captured on and which clock edge does the data change.
    //Refer to your microcontroller’s data sheet for the bit value for the clock phase.
    //According to this and referring to the data transfer waveform diagram provided in the datasheet
    //of LT2338 ADC IC it is found that the data has to be stable at the falling edge and can change at the
    // rising edge.
    //Referring to Table 18-3 on Pg 2060 of the technical refernce manual of F28379D, the appropriate settings is
    //Rising edge without delay
    //i.e. CLKPOLARITY 0 and CLK_PHASE 0
    SpiaRegs.SPICCR.bit.CLKPOLARITY = 0; //Based on the previous explanation
    SpiaRegs.SPICTL.bit.CLK_PHASE = 0; //Based on the previous explanation

    //Baud rate settings
    //Core clock at 200MHz
    //LSPCLK @100MHz
    EALLOW;
    ClkCfgRegs.LOSPCP.bit.LSPCLKDIV = 1; //LSPCLK = / 2 (default on reset)
    EDIS;
#if DataRate_2_5_MBPS
    SpiaRegs.SPIBRR.bit.SPI_BIT_RATE = 0x04; //SPI Baud Rate = LSPCLK/7 (20 MHz)
#endif

#if DataRate_2_0_MBPS
    SpiaRegs.SPIBRR.bit.SPI_BIT_RATE = 0x05; //SPI Baud Rate = LSPCLK/7 (16.66 MHz)
#endif

#if DataRate_1_7_MBPS
    SpiaRegs.SPIBRR.bit.SPI_BIT_RATE = 0x06; //SPI Baud Rate = LSPCLK/7 (14.28 MHz)
#endif
    SpiaRegs.SPICCR.bit.SPICHAR = 0xF; //16-bit word

    //Clear the flags
    SpiaRegs.SPISTS.bit.OVERRUN_FLAG = 1; //clear the SPI Receiver Overrun Flag

#if SPI_INT_ENABLE
    //Interrupt Settings
    SpiaRegs.SPICTL.bit.OVERRUNINTENA = 0x1; //Enable Receiver Overrun
    SpiaRegs.SPICTL.bit.SPIINTENA = 0x1; //Enable SPI Interrupt
#endif

    //SPI FIFO Settings

    SpiaRegs.SPIFFTX.all = 0xE000; //SPIFFTX = 1110 0000 0000 0000
    //SPIFFTX register Settings
    //Bit6: TX FIFO Interrupt Enable; Disable 0
    //Bit 7: TXFIFO Interrupt Clear; 1h (R/W) = Write 1 to clear SPIFFTX[TXFFINT] flag
    //Bit 13:TX FIFO Reset; Release transmit FIFO from reset
    //Bit 14: SPI FIFO Enhancements Enable; SPI FIFO enhancements are enabled.
    //Bit 15: SPI Reset ;SPI FIFO can resume transmit or receive. No effect to the SPI registers bits
    SpiaRegs.SPIFFRX.all = 0x6042; //SPIFFRX = 0110 0000 0100 0011
    //SPIFFRX register Settings
    //Bit 0-4: RXFFIL: Trigger interrupt after two receives
    //Bit 6: Receive FIFO Interrupt Clear; Write 1 to clear SPIFFRX[RXFFINT] flag
    //Bit 13: Receive FIFO Reset; Re-enable receive FIFO operation.
    //Bit 14: , RXFFOVFCLR; reset the overflow flag
    SpiaRegs.SPIFFCT.all = 0x0; //SPIFFCT = 0000 0000 0000 0000

    SpiaRegs.SPICCR.bit.SPICHAR = 0x8; //9-bit word

    
    //Reset Release
    SpiaRegs.SPICCR.bit.SPISWRESET = 1; //Release the SPI peripheral from RESET State
}



_interrupt void epwm1_isr(void)
{
    static volatile Uint16 GPIO34_count = 0;            // Counter for pin toggle

       PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;         // Must acknowledge the PIE group

       EPwm1Regs.ETCLR.bit.INT = 1; //clear the EPWM interrupt flag

       //Start a SPI data transmit
              //Pull the pin high; starts the conversion on the chip
              GpioDataRegs.GPASET.bit.GPIO19 = 1; //GPIO Set
              DelayUs(1);  //wait for 500 ns for conversion to take place
              GpioDataRegs.GPACLEAR.bit.GPIO19 = 1;  //GPIO Clear
              //SPI communication begins
              SpiaRegs.SPITXBUF=0x00;      // Send data. First dummy byte in FIFO
              SpiaRegs.SPITXBUF=0x00;      // Send data. Second dummy byte in FIFO

              //The above step automatically starts an SPI data transmit and a subsequent receive
              // WAIT FOR THE BYTE TO BE SENT AND THE OTHER BYTE TO BE RECEIVED AND PLACED 

//IN THE RXBUF REGISTER; Interrupt flag is raised after RXBUF has two bytes as specified in RXFFIL bit fields in RXFFST Register
              while(SpiaRegs.SPIFFRX.bit.RXFFST !=1);


              //Bit 13: Receive FIFO Reset; Re-enable receive FIFO operation.

              SpiaRegs.SPIFFRX.bit.RXFFINTCLR = 1;  //Clear the interrupt flag

              //Read the RXFIFO
              for (int i=0;i<2;i++)
              {
                  rxfifobuf[i] = SpiaRegs.SPIRXBUF;
              }

              SpiaRegs.SPIFFRX.bit.RXFIFORESET = 1; //Re-enable FIFO Receives

              //Reconstruct the ADC word by concatenating the ADC words
              temp = rxfifobuf[0];
              ADC_18bitval |= (temp<<9);
              temp = rxfifobuf[1];
              ADC_18bitval |= (temp<<0);

}

Any help would be greatly appreciated. Thank you once again.

Truly,

Kartikeya