TMS320F280049: CMPSS Minimal high-level hold time for a solid PWM Trip

Brian Wang0

Hi team,

I am confirming this for my customer:

What is the minimal hold time requirement for CMPSS to generate a solid PWM trip?

1. For example if a 3V on CMPSS positive input is regarded as a OC event which is connected to trigger PWM trip, what is the minimal hold time for this signal?

2. What if external input is used as PWM trip? What is the minimal hold time?

Sorry I did not notice any parameter on the datasheet talking about this.

Regards,

Brian

over 6 years ago

0 Subrahmanya over 6 years ago

TI__Mastermind 24095 points

Hi Brian,

Please refer to "Table 5-60. Trip-Zone Input Timing Requirements" in the device data sheet.
Timing requirement is similar in both cases.

0 Brian Wang0 over 6 years ago in reply to Subrahmanya

TI__Expert 5540 points

Hi Bhrathi,

I believe this is the case for digital TZ input.

Even for analog input CMPSS, the hold time would still be the same?

Regards,

Brian

0 Subrahmanya over 6 years ago in reply to Brian Wang0

TI__Mastermind 24095 points

Brian,

From a PWM standpoint - both the timings are similar. Note that even the digital TZ input could be coming from an external analog comparator.
So, the timing requirements are similar.

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TMS320F280049: CMPSS Minimal high-level hold time for a solid PWM Trip