TMS320F28388D: Setting clock divider for MCAN Clocking

Hi Dhanashree,

MCAN bit timing can be alternatively clocked using an auxiliary clock (AUXCLKIN).  This clock will feed the AUXPLL so AUXPLL should be configured with the correct multipliers and dividers so that it will meet the requirements stated in Table 5-11 (Internal Clock Frequencies) on the datasheet.  The output of the AUXPLLCLK can be prescaled using MCANCLKDIV and the resulting output will be used as the basis for MCAN bit timing.

Best regards,

Joseph

Hi Joseph,

So, as per my understanding, MCANCLKDIV will be used only when the MCAN clock source is an auxiliary clock. 

I have few more doubts related to a clocking of MCAN from above figure 45-3 (MCAN Integration):

1. If CM.CANx.SYSCLK is used for bit clocking then, what will be the role of the MCANCLKDIV? In the example 'mcan_ex1_loopback', the 'MCANABITCLKSEL is' set to '00'. which means the bit clock source is CMCLK/CPU1SYSCLK. But still, in configurations the MCANCLKDIV is explicitly set. Is there any reason behind it?

2. Also, could you please provide more details about when MCANABITCLKSEL is set to 00? Because if it is set to 0 then CMCLK/CPU1SYSCLK will be selected based on the PALLOCATE register setting. But, the PALLOCATE0 register does not have an MCAN field. 

Thanks,

Dhanashree