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TMS320F28379D: DMA behavior

CHRISTIAN VALPARD
Intellectual 340 points

Part Number: TMS320F28379D

Hi,

Please could you help me in the understanding of the DMA/CPU behavior.
In Figure 5-5 of SPRUHM8I we can see an HALT inside a burst of DMA (word pending in burst)
In §5.6 it's written "Suppose CPU accesses a peripheral / memory
causing conflict in middle of a DMA transfer, CPU is stalled till the current DMA access is complete and
not until the completion of whole DMA transfer."

What is the definition of "DMA access"? A burst or a word?
For a RAM access is it possible for the CPU to halt DMA Burst?

Best regards

C. VALPARD

  • 0
    TI__Guru** 116081 points

    Hi Christian,

     What is the definition of "DMA access"? A burst or a word?
    For a RAM access is it possible for the CPU to halt DMA Burst?

    DMA access here mean a READ or WRITE access from DMA. DMA has single interface for READ and WRITE so it does not perform back to back read or write to same memory. DMA burst means continuous transfer from DMA on a trigger till BURSTCOUNT is '0' (as per BURST_SIZE)  but since there will be idle cycle in between, pending CPU access (if there is one) will be granted access by RAM controller to specific RAM block.

    Hope this is clear.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    Intellectual 340 points

    Thank you very much again :-) Vivek

    Christian VALPARD