TMS320F28069M: Maximum ADC Clock is 90M or 45M?

Yamazaky,

You are correct that the effect of 0,0 in these bits will be that ADC Clock = System Clock.  If System clock is >45Mhz then this is unsupported configuration.  You will need to write to the CLKDIV2EN bit in this case to make the ADC clock 45MHz when System clock = 90MHz.

Best,

Matthew

Matthew,

if the SYSCLK is >45MHz, and CLKDIV are configured (0,0), what would happen to ADCCLK? Will ADCCLK be 45MHz?