TMS320F280049C: ePWM Global Load problem with deadtime and period load

Juraj Koys

Part Number: TMS320F280049C
Other Parts Discussed in Thread: C2000WARE

Hi All,

I am using microcontroller F280049C. I need to configure more parameters (TBPRD, TBPHS, CMPA, DBRED, DBFED) into more ePWM modules (ePWM1, ePWM2, ePWM3). I need to set all shadow registers and then load them all to active at the same time. Ideally when counters are at zero.

It works well when I just configure all shadow registers events to load new value at counter zero. However there is still a hazard when counter zero occurs in the middle of changing register values. Therefore I need to use global load in one shot mode. I configure all registers to be synchronized:

I have problem that loading DBRED, DBFED happens one counter cycle before also TBPRD is updated. I can’t find such issue documented in reference manual or errata. Here is what I do:

I also use EPWMXLINK to synchronize some registers among different ePWM modules.

The problem occurs when I change DBFED, DBRED times and also TBPRD at the same time. Here is what I get:

Green – TBPRD Counter value

Yellow – time when trigger one shot load GLDCTL2.bit.OSHTLD = 1

Red – ePWM1A

Blue – ePWM1B

Yellow arrow points to the moment when I change TBPRD and DBFED, DBRED to higher values. Then I trigger one shot load. As we can see the FED and RED are loaded to active when counter reach zero for the first time, but the TBPRD is set at next counter zero.

The same thing happens when I do it other way around:

I am attaching ePWM register values from debuger.

Could you please advice what am I doing wrong?

Thank you in advance.

Best Regards,

Juraj

over 4 years ago

0 Subrahmanya over 4 years ago

TI__Mastermind 24095 points

Hi,

Are you observing this on all the PWM instances or only on PWM1?
Are all other updates except DB in sync?

0 Juraj Koys over 4 years ago in reply to Subrahmanya

Intellectual 420 points

Yes, the same issue happens on all ePWMs (1, 2 and 3).

I only change TBPRD and DB for PWM1 and PWM2 (both have the same output signal shape). PWM3 is different.

If we look carefully it seems like the DB is synced in time in counter zero, but it is the period which is synced in following counter zero.

Green – TBPRD Counter value

Yellow – time when trigger one shot load GLDCTL2.bit.OSHTLD = 1

Red – ePWM1A, or ePWM2A (the same)

Blue – ePWM1B or ePWM2B (the same)

However I also set CMPA for PWM3. CMPA is updated at the same time as PRD . So the DB is again updated one period sooner. Here is the image:

Blue– TBPRD Counter value

Green – time when trigger one shot load GLDCTL2.bit.OSHTLD = 1

Red – ePWM3A

Yellow – ePWM3B

So it seems that DB is set in sync, but PRD and CMPA is set one period later.

I would expect opposite risk that updated DB could that effect one period later. According to the reference manual:

Do you have any ideas what could solve my problem?

Thanks in advance.

0 Subrahmanya over 4 years ago in reply to Juraj Koys

TI__Mastermind 24095 points

Hi,

Thank you for the details. The note regarding the DBRED/DBFED loading is only applicable to the case when the counters are counting.
In other occasions DBRED/DBFED would take effect immediately. Have you also configured DBRED/DBFED to be in shadow mode or immediate mode?
Note that the default mode is not shadow mode for DBRED/DBFED registers.
Please let us know the SHDWDBREDMODE in DBCTL register.

0 Juraj Koys over 4 years ago in reply to Subrahmanya

Intellectual 420 points

Hi,

thanks for the advice. I have already tried to set SHDWDBREDMODE and LOADREDMODE to all possible values and it does not make any difference as I remember. Currently I set SHDWDBREDMODE == 1 (Shadow mode ON) and LOADREDMODE == 3 (EPWM_RED_LOAD_FREEZE).

However the global load overrides individual load modes. Here is description of GLDCTL register - bit GLD.(which is set to 1)

0 Subrahmanya over 4 years ago in reply to Juraj Koys

TI__Mastermind 24095 points

Hi,

Thank you. As long as you do not place the registers (DB) in immediate load mode, this behavior is not expected.
You seem to have tried this already.
We are trying to replicate this at our end. If possible, please share the code - at least the PWM configuration for checking at our end.
We'll get back to you next week.

0 Juraj Koys over 4 years ago in reply to Subrahmanya

Intellectual 420 points

4857.register_values.txt

EPwm1Regs	EPWM Registers	
	TBCTL	0xA012	Time Base Control Register [Memory Mapped]	
	TBCTL2	0x0000	Time Base Control Register 2 [Memory Mapped]	
	TBCTR	0x001E	Time Base Counter Register [Memory Mapped]	
	TBSTS	0x0000	Time Base Status Register [Memory Mapped]	
	CMPCTL	0x0300	Counter Compare Control Register [Memory Mapped]	
	CMPCTL2	0x0000	Counter Compare Control Register 2 [Memory Mapped]	
	DBCTL	0x8FEB	Dead-Band Generator Control Register [Memory Mapped]	
	DBCTL2	0x0000	Dead-Band Generator Control Register 2 [Memory Mapped]	
	AQCTL	0x0000	Action Qualifier Control Register [Memory Mapped]	
	AQTSRCSEL	0x0000	Action Qualifier Trigger Event Source Select Register [Memory Mapped]	
	PCCTL	0x0000	PWM Chopper Control Register [Memory Mapped]	
	VCAPCTL	0x0000	Valley Capture Control Register [Memory Mapped]	
	VCNTCFG	0x0000	Valley Counter Config Register [Memory Mapped]	
	HRCNFG	0x0242	HRPWM Configuration Register [Memory Mapped]	
	HRPWR	0x0000	HRPWM Power Register [Memory Mapped]	
	HRMSTEP	0x0000	HRPWM MEP Step Register [Memory Mapped]	
	HRCNFG2	0x0000	HRPWM Configuration 2 Register [Memory Mapped]	
	HRPCTL	0x0001	High Resolution Period Control Register  [Memory Mapped]	
	TRREM	0x02FA	Translator High Resolution Remainder Register [Memory Mapped]	
	GLDCTL	0x0021	Global PWM Load Control Register [Memory Mapped]	
	GLDCFG	0x047F	Global PWM Load Config Register  [Memory Mapped]	
	EPWMXLINK	0x00000000	EPWMx Link Register [Memory Mapped]	
	AQCTLA	0x0006	Action Qualifier Control Register For Output A  [Memory Mapped]	
	AQCTLA2	0x0000	Additional Action Qualifier Control Register For Output A  [Memory Mapped]	
	AQCTLB	0x0006	Action Qualifier Control Register For Output B  [Memory Mapped]	
	AQCTLB2	0x0000	Additional Action Qualifier Control Register For Output B  [Memory Mapped]	
	AQSFRC	0x0000	Action Qualifier Software Force Register [Memory Mapped]	
	AQCSFRC	0x0000	Action Qualifier Continuous S/W Force Register  [Memory Mapped]	
	DBREDHR	0x0000	Dead-Band Generator Rising Edge Delay High Resolution Mirror Register  [Memory Mapped]	
	DBRED	0x001E	Dead-Band Generator Rising Edge Delay High Resolution Mirror Register  [Memory Mapped]	
	DBFEDHR	0xA600	Dead-Band Generator Falling Edge Delay High Resolution Register  [Memory Mapped]	
	DBFED	0x011C	Dead-Band Generator Falling Edge Delay Count Register [Memory Mapped]	
	TBPHS	0x00000000	Time Base Phase High [Memory Mapped]	
	TBPRDHR	0x9100	Time Base Period High Resolution Register  [Memory Mapped]	
	TBPRD	0x01A3	Time Base Period Register  [Memory Mapped]	
	CMPA	0x00000000	Counter Compare A Register  [Memory Mapped]	
	CMPB	0x00000000	Compare B Register  [Memory Mapped]	
	CMPC	0x0000	Counter Compare C Register [Memory Mapped]	
	CMPD	0x0000	Counter Compare D Register [Memory Mapped]	
	GLDCTL2	0x0000	Global PWM Load Control Register 2 [Memory Mapped]	
	SWVDELVAL	0x0000	Software Valley Mode Delay Register [Memory Mapped]	
	TZSEL	0x0000	Trip Zone Select Register  [Memory Mapped]	
	TZDCSEL	0x0000	Trip Zone Digital Comparator Select Register [Memory Mapped]	
	TZCTL	0x0000	Trip Zone Control Register [Memory Mapped]	
	TZCTL2	0x0000	Additional Trip Zone Control Register [Memory Mapped]	
	TZCTLDCA	0x0000	Trip Zone Control Register Digital Compare A  [Memory Mapped]	
	TZCTLDCB	0x0000	Trip Zone Control Register Digital Compare B  [Memory Mapped]	
	TZEINT	0x0000	Trip Zone Enable Interrupt Register [Memory Mapped]	
	TZFLG	0x0000	Trip Zone Flag Register [Memory Mapped]	
	TZCBCFLG	0x0000	Trip Zone CBC Flag Register [Memory Mapped]	
	TZOSTFLG	0x0000	Trip Zone OST Flag Register [Memory Mapped]	
	TZCLR	0x0000	Trip Zone Clear Register [Memory Mapped]	
	TZCBCCLR	0x0000	Trip Zone CBC Clear Register [Memory Mapped]	
	TZOSTCLR	0x0000	Trip Zone OST Clear Register [Memory Mapped]	
	TZFRC	0x0000	Trip Zone Force Register [Memory Mapped]	
	ETSEL	0x0000	Event Trigger Selection Register [Memory Mapped]	
	ETPS	0x0000	Event Trigger Pre-Scale Register [Memory Mapped]	
	ETFLG	0x0000	Event Trigger Flag Register [Memory Mapped]	
	ETCLR	0x0000	Event Trigger Clear Register [Memory Mapped]	
	ETFRC	0x0000	Event Trigger Force Register [Memory Mapped]	
	ETINTPS	0x0000	Event-Trigger Interrupt Pre-Scale Register [Memory Mapped]	
	ETSOCPS	0x0000	Event-Trigger SOC Pre-Scale Register [Memory Mapped]	
	ETCNTINITCTL	0x0000	Event-Trigger Counter Initialization Control Register [Memory Mapped]	
	ETCNTINIT	0x0000	Event-Trigger Counter Initialization Register [Memory Mapped]	
	DCTRIPSEL	0x0000	Digital Compare Trip Select Register [Memory Mapped]	
	DCACTL	0x0000	Digital Compare A Control Register [Memory Mapped]	
	DCBCTL	0x0000	Digital Compare B Control Register [Memory Mapped]	
	DCFCTL	0x0000	Digital Compare Filter Control Register [Memory Mapped]	
	DCCAPCTL	0x0000	Digital Compare Capture Control Register [Memory Mapped]	
	DCFOFFSET	0x0000	Digital Compare Filter Offset Register  [Memory Mapped]	
	DCFOFFSETCNT	0x0000	Digital Compare Filter Offset Counter Register [Memory Mapped]	
	DCFWINDOW	0x0000	Digital Compare Filter Window Register [Memory Mapped]	
	DCFWINDOWCNT	0x0000	Digital Compare Filter Window Counter Register [Memory Mapped]	
	DCCAP	0x0000	Digital Compare Counter Capture Register  [Memory Mapped]	
	DCAHTRIPSEL	0x0000	Digital Compare AH Trip Select  [Memory Mapped]	
	DCALTRIPSEL	0x0000	Digital Compare AL Trip Select  [Memory Mapped]	
	DCBHTRIPSEL	0x0000	Digital Compare BH Trip Select  [Memory Mapped]	
	DCBLTRIPSEL	0x0000	Digital Compare BL Trip Select  [Memory Mapped]	
	EPWMLOCK	0x0000001F	EPWM Lock Register [Memory Mapped]	
	HWVDELVAL	0x0000	Hardware Valley Mode Delay Register [Memory Mapped]	
	VCNTVAL	0x0000	Hardware Valley Counter Register [Memory Mapped]	
	
EPwm2Regs	EPWM Registers	
	TBCTL	0xA002	Time Base Control Register [Memory Mapped]	
	TBCTL2	0x0000	Time Base Control Register 2 [Memory Mapped]	
	TBCTR	0x0021	Time Base Counter Register [Memory Mapped]	
	TBSTS	0x0003	Time Base Status Register [Memory Mapped]	
	CMPCTL	0x0300	Counter Compare Control Register [Memory Mapped]	
	CMPCTL2	0x0000	Counter Compare Control Register 2 [Memory Mapped]	
	DBCTL	0xBFEB	Dead-Band Generator Control Register [Memory Mapped]	
	DBCTL2	0x0000	Dead-Band Generator Control Register 2 [Memory Mapped]	
	AQCTL	0x0000	Action Qualifier Control Register [Memory Mapped]	
	AQTSRCSEL	0x0000	Action Qualifier Trigger Event Source Select Register [Memory Mapped]	
	PCCTL	0x0000	PWM Chopper Control Register [Memory Mapped]	
	VCAPCTL	0x0000	Valley Capture Control Register [Memory Mapped]	
	VCNTCFG	0x0000	Valley Counter Config Register [Memory Mapped]	
	HRCNFG	0x0242	HRPWM Configuration Register [Memory Mapped]	
	HRPWR	0x0000	HRPWM Power Register [Memory Mapped]	
	HRMSTEP	0x0000	HRPWM MEP Step Register [Memory Mapped]	
	HRCNFG2	0x0000	HRPWM Configuration 2 Register [Memory Mapped]	
	HRPCTL	0x0001	High Resolution Period Control Register  [Memory Mapped]	
	TRREM	0x0152	Translator High Resolution Remainder Register [Memory Mapped]	
	GLDCTL	0x0021	Global PWM Load Control Register [Memory Mapped]	
	GLDCFG	0x047F	Global PWM Load Config Register  [Memory Mapped]	
	EPWMXLINK	0x00011110	EPWMx Link Register [Memory Mapped]	
	AQCTLA	0x0006	Action Qualifier Control Register For Output A  [Memory Mapped]	
	AQCTLA2	0x0000	Additional Action Qualifier Control Register For Output A  [Memory Mapped]	
	AQCTLB	0x0006	Action Qualifier Control Register For Output B  [Memory Mapped]	
	AQCTLB2	0x0000	Additional Action Qualifier Control Register For Output B  [Memory Mapped]	
	AQSFRC	0x0000	Action Qualifier Software Force Register [Memory Mapped]	
	AQCSFRC	0x0000	Action Qualifier Continuous S/W Force Register  [Memory Mapped]	
	DBREDHR	0x0000	Dead-Band Generator Rising Edge Delay High Resolution Mirror Register  [Memory Mapped]	
	DBRED	0x001E	Dead-Band Generator Rising Edge Delay High Resolution Mirror Register  [Memory Mapped]	
	DBFEDHR	0x0000	Dead-Band Generator Falling Edge Delay High Resolution Register  [Memory Mapped]	
	DBFED	0x001E	Dead-Band Generator Falling Edge Delay Count Register [Memory Mapped]	
	TBPHS	0x00000000	Time Base Phase High [Memory Mapped]	
	TBPRDHR	0x0600	Time Base Period High Resolution Register  [Memory Mapped]	
	TBPRD	0x02F7	Time Base Period Register  [Memory Mapped]	
	CMPA	0x00000000	Counter Compare A Register  [Memory Mapped]	
	CMPB	0x00000000	Compare B Register  [Memory Mapped]	
	CMPC	0x0000	Counter Compare C Register [Memory Mapped]	
	CMPD	0x0000	Counter Compare D Register [Memory Mapped]	
	GLDCTL2	0x0000	Global PWM Load Control Register 2 [Memory Mapped]	
	SWVDELVAL	0x0000	Software Valley Mode Delay Register [Memory Mapped]	
	TZSEL	0x0000	Trip Zone Select Register  [Memory Mapped]	
	TZDCSEL	0x0000	Trip Zone Digital Comparator Select Register [Memory Mapped]	
	TZCTL	0x0000	Trip Zone Control Register [Memory Mapped]	
	TZCTL2	0x0000	Additional Trip Zone Control Register [Memory Mapped]	
	TZCTLDCA	0x0000	Trip Zone Control Register Digital Compare A  [Memory Mapped]	
	TZCTLDCB	0x0000	Trip Zone Control Register Digital Compare B  [Memory Mapped]	
	TZEINT	0x0000	Trip Zone Enable Interrupt Register [Memory Mapped]	
	TZFLG	0x0000	Trip Zone Flag Register [Memory Mapped]	
	TZCBCFLG	0x0000	Trip Zone CBC Flag Register [Memory Mapped]	
	TZOSTFLG	0x0000	Trip Zone OST Flag Register [Memory Mapped]	
	TZCLR	0x0000	Trip Zone Clear Register [Memory Mapped]	
	TZCBCCLR	0x0000	Trip Zone CBC Clear Register [Memory Mapped]	
	TZOSTCLR	0x0000	Trip Zone OST Clear Register [Memory Mapped]	
	TZFRC	0x0000	Trip Zone Force Register [Memory Mapped]	
	ETSEL	0x0000	Event Trigger Selection Register [Memory Mapped]	
	ETPS	0x0000	Event Trigger Pre-Scale Register [Memory Mapped]	
	ETFLG	0x0000	Event Trigger Flag Register [Memory Mapped]	
	ETCLR	0x0000	Event Trigger Clear Register [Memory Mapped]	
	ETFRC	0x0000	Event Trigger Force Register [Memory Mapped]	
	ETINTPS	0x0000	Event-Trigger Interrupt Pre-Scale Register [Memory Mapped]	
	ETSOCPS	0x0000	Event-Trigger SOC Pre-Scale Register [Memory Mapped]	
	ETCNTINITCTL	0x0000	Event-Trigger Counter Initialization Control Register [Memory Mapped]	
	ETCNTINIT	0x0000	Event-Trigger Counter Initialization Register [Memory Mapped]	
	DCTRIPSEL	0x0000	Digital Compare Trip Select Register [Memory Mapped]	
	DCACTL	0x0000	Digital Compare A Control Register [Memory Mapped]	
	DCBCTL	0x0000	Digital Compare B Control Register [Memory Mapped]	
	DCFCTL	0x0000	Digital Compare Filter Control Register [Memory Mapped]	
	DCCAPCTL	0x0000	Digital Compare Capture Control Register [Memory Mapped]	
	DCFOFFSET	0x0000	Digital Compare Filter Offset Register  [Memory Mapped]	
	DCFOFFSETCNT	0x0000	Digital Compare Filter Offset Counter Register [Memory Mapped]	
	DCFWINDOW	0x0000	Digital Compare Filter Window Register [Memory Mapped]	
	DCFWINDOWCNT	0x0000	Digital Compare Filter Window Counter Register [Memory Mapped]	
	DCCAP	0x0000	Digital Compare Counter Capture Register  [Memory Mapped]	
	DCAHTRIPSEL	0x0000	Digital Compare AH Trip Select  [Memory Mapped]	
	DCALTRIPSEL	0x0000	Digital Compare AL Trip Select  [Memory Mapped]	
	DCBHTRIPSEL	0x0000	Digital Compare BH Trip Select  [Memory Mapped]	
	DCBLTRIPSEL	0x0000	Digital Compare BL Trip Select  [Memory Mapped]	
	EPWMLOCK	0x0000001F	EPWM Lock Register [Memory Mapped]	
	HWVDELVAL	0x0000	Hardware Valley Mode Delay Register [Memory Mapped]	
	VCNTVAL	0x0000	Hardware Valley Counter Register [Memory Mapped]
	
EPwm3Regs	EPWM Registers	
	TBCTL	0xA002	Time Base Control Register [Memory Mapped]	
	TBCTL2	0x0000	Time Base Control Register 2 [Memory Mapped]	
	TBCTR	0x0163	Time Base Counter Register [Memory Mapped]	
	TBSTS	0x0002	Time Base Status Register [Memory Mapped]	
	CMPCTL	0x0300	Counter Compare Control Register [Memory Mapped]	
	CMPCTL2	0x0000	Counter Compare Control Register 2 [Memory Mapped]	
	DBCTL	0x8FEB	Dead-Band Generator Control Register [Memory Mapped]	
	DBCTL2	0x0000	Dead-Band Generator Control Register 2 [Memory Mapped]	
	AQCTL	0x0000	Action Qualifier Control Register [Memory Mapped]	
	AQTSRCSEL	0x0000	Action Qualifier Trigger Event Source Select Register [Memory Mapped]	
	PCCTL	0x0000	PWM Chopper Control Register [Memory Mapped]	
	VCAPCTL	0x0000	Valley Capture Control Register [Memory Mapped]	
	VCNTCFG	0x0000	Valley Counter Config Register [Memory Mapped]	
	HRCNFG	0x0242	HRPWM Configuration Register [Memory Mapped]	
	HRPWR	0x0000	HRPWM Power Register [Memory Mapped]	
	HRMSTEP	0x0000	HRPWM MEP Step Register [Memory Mapped]	
	HRCNFG2	0x0000	HRPWM Configuration 2 Register [Memory Mapped]	
	HRPCTL	0x0001	High Resolution Period Control Register  [Memory Mapped]	
	TRREM	0x02B2	Translator High Resolution Remainder Register [Memory Mapped]	
	GLDCTL	0x0021	Global PWM Load Control Register [Memory Mapped]	
	GLDCFG	0x047F	Global PWM Load Config Register  [Memory Mapped]	
	EPWMXLINK	0x00022220	EPWMx Link Register [Memory Mapped]	
	AQCTLA	0x0012	Action Qualifier Control Register For Output A  [Memory Mapped]	
	AQCTLA2	0x0000	Additional Action Qualifier Control Register For Output A  [Memory Mapped]	
	AQCTLB	0x0804	Action Qualifier Control Register For Output B  [Memory Mapped]	
	AQCTLB2	0x0000	Additional Action Qualifier Control Register For Output B  [Memory Mapped]	
	AQSFRC	0x0000	Action Qualifier Software Force Register [Memory Mapped]	
	AQCSFRC	0x0000	Action Qualifier Continuous S/W Force Register  [Memory Mapped]	
	DBREDHR	0xA600	Dead-Band Generator Rising Edge Delay High Resolution Mirror Register  [Memory Mapped]	
	DBRED	0x011C	Dead-Band Generator Rising Edge Delay High Resolution Mirror Register  [Memory Mapped]	
	DBFEDHR	0x0000	Dead-Band Generator Falling Edge Delay High Resolution Register  [Memory Mapped]	
	DBFED	0x001E	Dead-Band Generator Falling Edge Delay Count Register [Memory Mapped]	
	TBPHS	0x00000000	Time Base Phase High [Memory Mapped]	
	TBPRDHR	0x9100	Time Base Period High Resolution Register  [Memory Mapped]	
	TBPRD	0x01A3	Time Base Period Register  [Memory Mapped]	
	CMPA	0x02C5B000	Counter Compare A Register  [Memory Mapped]	
	CMPB	0x00315600	Compare B Register  [Memory Mapped]	
	CMPC	0x0000	Counter Compare C Register [Memory Mapped]	
	CMPD	0x0000	Counter Compare D Register [Memory Mapped]	
	GLDCTL2	0x0000	Global PWM Load Control Register 2 [Memory Mapped]	
	SWVDELVAL	0x0000	Software Valley Mode Delay Register [Memory Mapped]	
	TZSEL	0x0000	Trip Zone Select Register  [Memory Mapped]	
	TZDCSEL	0x0000	Trip Zone Digital Comparator Select Register [Memory Mapped]	
	TZCTL	0x0000	Trip Zone Control Register [Memory Mapped]	
	TZCTL2	0x0000	Additional Trip Zone Control Register [Memory Mapped]	
	TZCTLDCA	0x0000	Trip Zone Control Register Digital Compare A  [Memory Mapped]	
	TZCTLDCB	0x0000	Trip Zone Control Register Digital Compare B  [Memory Mapped]	
	TZEINT	0x0000	Trip Zone Enable Interrupt Register [Memory Mapped]	
	TZFLG	0x0000	Trip Zone Flag Register [Memory Mapped]	
	TZCBCFLG	0x0000	Trip Zone CBC Flag Register [Memory Mapped]	
	TZOSTFLG	0x0000	Trip Zone OST Flag Register [Memory Mapped]	
	TZCLR	0x0000	Trip Zone Clear Register [Memory Mapped]	
	TZCBCCLR	0x0000	Trip Zone CBC Clear Register [Memory Mapped]	
	TZOSTCLR	0x0000	Trip Zone OST Clear Register [Memory Mapped]	
	TZFRC	0x0000	Trip Zone Force Register [Memory Mapped]	
	ETSEL	0x0000	Event Trigger Selection Register [Memory Mapped]	
	ETPS	0x0000	Event Trigger Pre-Scale Register [Memory Mapped]	
	ETFLG	0x0000	Event Trigger Flag Register [Memory Mapped]	
	ETCLR	0x0000	Event Trigger Clear Register [Memory Mapped]	
	ETFRC	0x0000	Event Trigger Force Register [Memory Mapped]	
	ETINTPS	0x0000	Event-Trigger Interrupt Pre-Scale Register [Memory Mapped]	
	ETSOCPS	0x0000	Event-Trigger SOC Pre-Scale Register [Memory Mapped]	
	ETCNTINITCTL	0x0000	Event-Trigger Counter Initialization Control Register [Memory Mapped]	
	ETCNTINIT	0x0000	Event-Trigger Counter Initialization Register [Memory Mapped]	
	DCTRIPSEL	0x0000	Digital Compare Trip Select Register [Memory Mapped]	
	DCACTL	0x0000	Digital Compare A Control Register [Memory Mapped]	
	DCBCTL	0x0000	Digital Compare B Control Register [Memory Mapped]	
	DCFCTL	0x0000	Digital Compare Filter Control Register [Memory Mapped]	
	DCCAPCTL	0x0000	Digital Compare Capture Control Register [Memory Mapped]	
	DCFOFFSET	0x0000	Digital Compare Filter Offset Register  [Memory Mapped]	
	DCFOFFSETCNT	0x0000	Digital Compare Filter Offset Counter Register [Memory Mapped]	
	DCFWINDOW	0x0000	Digital Compare Filter Window Register [Memory Mapped]	
	DCFWINDOWCNT	0x0000	Digital Compare Filter Window Counter Register [Memory Mapped]	
	DCCAP	0x0000	Digital Compare Counter Capture Register  [Memory Mapped]	
	DCAHTRIPSEL	0x0000	Digital Compare AH Trip Select  [Memory Mapped]	
	DCALTRIPSEL	0x0000	Digital Compare AL Trip Select  [Memory Mapped]	
	DCBHTRIPSEL	0x0000	Digital Compare BH Trip Select  [Memory Mapped]	
	DCBLTRIPSEL	0x0000	Digital Compare BL Trip Select  [Memory Mapped]	
	EPWMLOCK	0x0000001F	EPWM Lock Register [Memory Mapped]	
	HWVDELVAL	0x0000	Hardware Valley Mode Delay Register [Memory Mapped]	
	VCNTVAL	0x0000	Hardware Valley Counter Register [Memory Mapped]

Hi,

thanks for your effort. I am not using immediate load mode as far as I know.

I am attaching all register values of PWM1,2,3 = my configuration.

In CLA interrupt I change PWM period and DB every period. Here is the source:

#define SET_DEADTIME(T_DEAD) {EPwm1Regs.DBRED.all = T_DEAD; EPwm2Regs.DBRED.all = T_DEAD; EPwm3Regs.DBRED.all = T_DEAD; EPwm1Regs.DBFED.all = T_DEAD; EPwm2Regs.DBFED.all = T_DEAD; EPwm3Regs.DBFED.all = T_DEAD;}

__attribute__((interrupt)) void Cla1Task1 ( void )
{

...

SET_DEADTIME(ulTdead);

EPwm1Regs.TBPRD.all = slTsw << 8; // period
EPwm3Regs.CMPA.all = EPwm1Regs.TBPRD.all - slHrpwm_500ns; // shutdown sooner

EPwm1Regs.GLDCTL2.bit.OSHTLD = 1;

...

}

I run all PWMs at 180kHz with deadTime 150ns. Then I change PWM frequency to 65kHz with deadtime 1500ns. Then several periods later I set the frequency and deadtime back to 180kHz and 150ns. Every time I do a change the inconsistency of PRD and DT occurs.

0 Subrahmanya over 4 years ago in reply to Juraj Koys

TI__Mastermind 24095 points

Hi,

I've tried to create this condition and I'm unable to see the issue you've experienced.
I've used the Global load one shot mode and varied period and deadband values on the fly.
I also maintain 50% duty by updating the CMPA value when I change the frequency.
I see that they are in sync and dead band is getting applied as expected.
What is your PWM configuration? What events are used to set and clear the PWM?

0 Subrahmanya over 4 years ago in reply to Subrahmanya

TI__Mastermind 24095 points

Hi,

You've attached the hex values of regs, but it doesn't give me an idea of when the updates are being applied and when they are captured.
Is it possible to add the configuration code, with the updates etc.?
Other option is if you can start with an existing test case below.
C:\ti\c2000\C2000Ware_3_02_00_00\device_support\f2837xd\examples\cpu1\hrpwm_deadband_sfo_v8\cpu01
If you can start with this, we can replicate easily debug the issue quickly.

0 Juraj Koys over 4 years ago in reply to Subrahmanya

Intellectual 420 points

Hi,

thanks for your effort. Yes, you can see the PWM configuration values in the attached text file. You can also see the time when the update is made is marked in the osciloscope screen with green color:

However I am afraid that you are using wrong device to reproduce the issue. You mentioned example program that path is for f2837xd and I am using f28004x could this be the problem that prevent you from reproduction of the issue? Or is the ePWM periphery exactly the same at f2837xd and f28004x?

I think maybe this example could be closer:

C2000Ware_3_02_00_00_Software\device_support\f28004x\examples\hrpwm

What do you think?

0 Juraj Koys over 4 years ago in reply to Subrahmanya

Intellectual 420 points

We have compared the f2837xd and f28004x ePWM and HRPWM modules.

It seems like there is a mistake in the documentation. If I compare following tables, it seems like HRPWM module is different.

However we check following table it says the HRPWM type is the same:

So which one is correct?

0 Subrahmanya over 4 years ago in reply to Juraj Koys

TI__Mastermind 24095 points

Hi,

Both the devices have same HRPWM type. Table 15 above seems to be incorrect.
The deadband example was I pointed to you earlier was available on F2837x folder only, since you are using the deadband i've pointed you to the example.
I would not expect difference of behavior w.r.t. this function between these devices.

0 Subrahmanya over 4 years ago

TI__Mastermind 24095 points

Hello,
I looked at the debugger values you provided and I do not see anything incorrect.
So, only thing I can suspect is the timing of the register updates - though you've indicated in the waveform diagram, that may be a place where there is inconsistency in the setup. Did you get a chance to check with the example provided? Do you observe a similar behavior?
In my set up, I started with the example and instead of continuously updating, i switch between 2 different sets of values (CMPx, TBPRD, DBRED/fED). Updates seem to be in sync in that test condition.

0 Juraj Koys over 4 years ago in reply to Subrahmanya

Intellectual 420 points

Hi,

It should not be a timing issue of register updates. I only set shadow registers. Global load should ensure that all selected registers are loaded from shadow to active simultaneously. It should not matter on timing when I trigger global load by setting OSHLD = 1 because the update should happen only when OSHLD == 1 and also TBCTR == ZERO . So it should happen everytime in the same moment. The update should not happen in any other time. Otherwise global load functionality does not fulfill its purpose.

Sorry, I had no time to check the example.

0 Subrahmanya over 4 years ago in reply to Juraj Koys

TI__Mastermind 24095 points

Hi,

We could recreate the issue you've mentioned above. The difference in timing is occurring when HRPCTL is set to 1.
If this is disabled, all the register updates are in sync. In my earlier trials i was using global one-shot load but not with HRPCTL=1, hence the register updates were in sync. Do you need HR period control for your application?
If so, this difference in loading is occurring w.r.t. TBPRD/CMPx register loading vs. DBRED/FED register loading.
One workaround, i can think to overcome this, is to not use global one-shot loading for deadband registers.
Update the TBPRD/CMPA/B registers, then take the following counter zero interrupt and update the DBRED/FED registers.
This will ensure that all the register updates are in sync.

0 Juraj Koys over 4 years ago in reply to Subrahmanya

Intellectual 420 points

Hi,

I have already prepared an example that reproduce the issue. I am glad to hear that you reproduced it too.

Yes, I confirm, it works correctly if HRPWM is not used.

Yes, It also works mostly correctly if I do not use global load feature.

Unfortunatelly I need HRPWM and also Global load feature in order to avoid hazard states because I am synchronizing 5 different PWMs with more than one parameter.

My current workaround is that I set TBPRD/CMPx immediatelly and then set DBRED/FED one period later, which significantly delays my regulation.

If I update DBRED/FED registers in zero interrupt I have the same delay of regulation anyway, because it is the TBPRD/CMPx that are updated later than necessary. Also there is another hazard that RED/FED counters are already running and the new value will be used next period anyway. According to:

Is there any hardware fix for this PRD vs. DB synchronization? Any new HW release? Is this problem present at all ePWM devices type 4 in all microcontrollers with this periphery?

0 Subrahmanya over 4 years ago in reply to Juraj Koys

TI__Mastermind 24095 points

Hi,

Juraj Koys said:
Is there any hardware fix for this PRD vs. DB synchronization? Any new HW release? Is this problem present at all ePWM devices type 4 in all microcontrollers with this periphery?

Yes, this mismatch in the timing of registers in the DB vs PRD/CMPx registers, with HRPCTL enable is there on all type-4, with global load option.
Currently, only way to work around this is to update use counter zero interrupt to update DBCTL following the TBPRD/CMPx global load.

Juraj Koys said:
Also there is another hazard that RED/FED counters are already running and the new value will be used next period anyway.

Yes, if the counters are already progressing then the values will take effect only in the following cycle.
Is this a possibility in your scenarios - update happening while DB counters are counting?

0 Juraj Koys over 4 years ago in reply to Subrahmanya

Intellectual 420 points

Actually If I set DBFED/RED in counter zero interrupt, it does not really help much. The problem is that PRD/CMPx registers takes place one period later than requested. So I also have to set DBFED/RED one period later than intended. So It makes my regulation slower by one more PWM period which may cause higher instability.

As we can see DBFED/RED are updated sooner than PRD/CMPx so I think I am not updating the DB registers while they are counting.

Lets forget about DBRED/FED registers. Summary is if we ommit the DB registers. The update of get PRD/CMPx is still one period later than expected which makes my regulation cycle slower. I need to use OSHLD and HRPWM.

Do you have any better idea how to avoid this?

0 Subrahmanya over 4 years ago in reply to Juraj Koys

TI__Mastermind 24095 points

Hi,

I agree, even if we leave aside DBRED/FED regs, there is a delay in the register update with HR registers in Global load mode.
Only option to avoid that delay would be to not use Global/OSHTLD loading option.
Would it be possible to update the registers in normal mode (not global) using an ISR to time the updates as needed?
Is your concern about not being able to update all the registers in an ISR?
Why is the global load option a must have in this case? Maybe we can work around that requirement in a different way, optimize the code etc.

0 Juraj Koys over 4 years ago in reply to Subrahmanya

Intellectual 420 points

Thank you for the explanations.

The source code is optimal. I only wanted to use global OSHLD mode to ensure that all values are always synchronized without any hazard without using any ISR.

0 Genatco over 4 years ago in reply to Juraj Koys

Guru 54648 points

Hi Juraj,

Following this thread and holding comments until now. On another MCU class it can set global synchronous updates for the PWM generator period. And configure local NoSync (immediate) updates of dead band RED/FED registers serviced by the same interrupt. It would seem odd for global updates of dead band as that is often tied to count time out in most PWM generators. NFET turn off (shoot through) may result after the fact of gen count timeout when global count updates assert.

Testing dead band with global updates; the DC inverter produced odd waveform and SPM motor did not like it either.

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TMS320F280049C: ePWM Global Load problem with deadtime and period load