interrupt PWM1 less priority than TIMER1 and 2 ???

Dear all, I'm designing a program on TMS320F23023, which needs to use three interrupts functions handlers to manage tree ISRs: My problem is about the page 121 in the document SPRUFN3C.pdf, there is a table about the PIE vector Table in which we can see: CPU priority - PWM1 ISR @ 300Khz INT3.1 6.1 //this task run in RAM and must be handle every time! - TIMER 1 ISR @ 1/200µs INT13 17 //this task run in Flash - TIMER 2 ISR @ 1/20ms INT14 18 //this task run in Flash Whereas, when the TIMER 1 ISR is handling and the PWM1 ISR occurs it isn't handle and a second PWM1 ISR is needed to handle it! The same thing’ve happened So I don't understand why PWM1 ISR hasn't the most priority? How I init the TIMER 1: /*initialization of timer1*/ TIMER_init ( &timer1, TIMER1 ); TIMER_set_handler ( & timer1, _handler_TIM1 ); TIMER_config ( &timer_1, CPU_FREQ/1E6, l_U32_periodTimer ); TIMER_enable ( &timer_1 ); How I handle the ISR : TIMER EALLOW; EINT; asm(" NOP"); asm(" NOP"); timer[1]->InterruptCount++; // The CPU acknowledges the interrupt. EDIS; timer[1]->handler(); How I init the PWM interrupt: EALLOW; // This is needed to write to EALLOW protected registers PieVectTable.EPWM1_INT = pwm_hdl; EDIS; // This is needed to disable write to EALLOW protected registers //Enable EPWM INTn in the PIE: Group 3 interrupt 1-3 PieCtrlRegs.PIEIER3.bit.INTx1 = 1; PieCtrlRegs.PIEIER3.bit.INTx2 = 1; //Enable CPU INT3 which is connected to EPWM1-3 INT: IER |= M_INT3; // Enable CPU Interrupt 1 EALLOW; SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; EDIS; How I handle the ISR : TIMER ESTOP0; DINT; EPwm1Regs.ETCLR.bit.INT = 1; // acknowledge this interrupt to receive more interrupts from group 3 PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; EINT; Thanks for your help,