• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Answers 1 answer
  • Subscribers 82 subscribers
  • Views 1498 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F28069M: SCI UART baud rate tolerance

Jacky Romano
Prodigy 60 points

Part Number: TMS320F28069M
Other Parts Discussed in Thread: TMS320F28069

Hi,

I'm trying to figure out what is the maximum baudrate difference allowed between CSI transmitter and receiver?

Can someone point me to such specification? 

I couldn't find any in:

https://www.ti.com/lit/ug/spruh18h/spruh18h.pdf?ts=1598990234821&ref_url=https%253A%252F%252Fwww.google.com%252F

Thanks in advance,

Jacky

  • 0
    TI__Mastermind 26110 points

    Hi Jacky,

    We do not release a spec for the maximum baudrate difference allowed between transmitter and receiver.

    However, the TMS320F28069 device does have a programmable baud rate with up to 64K different rates. Hopefully with the vast amount of options you can find one closest to your required baud rate.

    Later this year we are also releasing a software example that will show how to tune the baud rate of the device to the incoming baud rate. 

    Best Regards,

    Marlyn

  • 0 in reply to Marlyn Rosales Castaneda20
    Prodigy 60 points

    Hi Marlyn,

    Many thanks for your prompt reply. In my application we are going to connect a custom chip to a F28xx based boards and the question that came up is what is allowed deviation between the custom chip and the F28xx baud rates? Can we assume that the F28xx SCI hardware samples the data bit at the middle of bit period so up clock difference < 3% is acceptable? The chips are about 20 cm apart and rates we are planing are 460,800.

    Thanks,

    Jacky

  • 0 in reply to Jacky Romano
    TI__Mastermind 26110 points

    Hi Jacky,

    Jacky Romano said:
    Can we assume that the F28xx SCI hardware samples the data bit at the middle of bit period so up clock difference < 3% is acceptable?

    Yes, the SCI hardware samples the date bit at the middle of the bit period. You want to make sure that the last data bit is sampled within its bit period (ex. somewhere between the 50% to 80% of the bit period)  before the stop bit. Depending on what you choose that margin to be your % of tolerance will change but <3% sounds acceptable for your desired baud rate.    

    Depending on your LSPCLK you can calculate what to set the BRR register to. If your LSPCLK is 100MHz for example then the following calculation is true.

    BRR= LSPCLK/(SCI Async Baud *8)-1

    For your ideal baud rate of 460800, you would need to set the BRR register to 26, giving you a percent error of .47 from the ideal baud rate to the actual for the F28xx device.  

    The distance between the devices is not factored into the above nor is the % error of baud rate from the custom chip but even then I think you should be within the <3% tolerance.

    Best Regards,

    Marlyn

  • 0 in reply to Marlyn Rosales Castaneda20
    Prodigy 60 points

    many thanks !!

    That covers all the information I needed.