Part Number: LAUNCHXL-F28379D
Tool/software: Code Composer Studio
I am trying to use comparators (CMPSS) to activate the ADCs in CPU2 but it is not working for me I attach code:
CP1:
// Este es el primer proyecto en el que se va a integrar la comunicacion entre las dos CPU via RAM compartida
//Para ello utilizaremos Dos registros GS0 yGS1´
//
//Includes
//
#include "driverlib.h"
#include "device.h"
#include "F2837xD_Ipc_drivers.h"
//
//Globall
//
uint16_t ReadArry[256];
uint16_t WriteArry[256];
#pragma DATA_SECTION(ReadArry, "SHARERAMGS0");
#pragma DATA_SECTION(WriteArry, "SHARERAMGS1");
uint16_t error;
uint16_t count=0;
uint16_t multiplier;
extern uint16_t isrfuncLoadStart;
extern uint16_t isrfuncLoadEnd;
extern uint16_t isrfuncRunStart;
extern uint16_t isrfuncLoadSize;
//
//Funciones
//
void initCputimer(uint32_t);
void configCputimer(uint32_t,float,float);
__interrupt void cpuTimer0ISR(void);
#pragma CODE_SECTION(cpuTimer0ISR,"isrfunc");
void leerdato(void);
void escribirdato(void);
void initCMPSS(void);
/**
* main.c
*/
int main(void)
{
Device_init();
Device_initGPIO();
//Configuracion push-pull y output
GPIO_setPadConfig(DEVICE_GPIO_PIN_LED1, GPIO_PIN_TYPE_STD);
GPIO_setDirectionMode(DEVICE_GPIO_PIN_LED1, GPIO_DIR_MODE_OUT);
GPIO_setPadConfig(DEVICE_GPIO_PIN_LED2, GPIO_PIN_TYPE_STD);
GPIO_setDirectionMode(DEVICE_GPIO_PIN_LED2, GPIO_DIR_MODE_OUT);
//configuracion del master
GPIO_setMasterCore(DEVICE_GPIO_PIN_LED1, GPIO_CORE_CPU2);
GPIO_setMasterCore(DEVICE_GPIO_PIN_LED2, GPIO_CORE_CPU1);
Interrupt_initModule();
Interrupt_initVectorTable();
MemCfg_setGSRAMMasterSel((MEMCFG_SECT_GS0 | MEMCFG_SECT_GS14),
MEMCFG_GSRAMMASTER_CPU2);
memcpy(&isrfuncRunStart, &isrfuncLoadStart, (uint32_t)&isrfuncLoadSize);
//
// Interrupts that are used in this example are re-mapped to ISR functions
// found within this file.
//
Interrupt_register(INT_TIMER0, &cpuTimer0ISR);
//
// Configure CPU Timer 0 to a 2 second period
//
//initCputimer(CPUTIMER0_BASE);
configCputimer(CPUTIMER0_BASE, DEVICE_SYSCLK_FREQ, 2000000);
CPUTimer_startTimer(CPUTIMER0_BASE);
Interrupt_enable(INT_TIMER0);
EINT;
ERTM;
error=0;
multiplier = 0;
EALLOW;
DevCfgRegs.CPUSEL11.bit.ADC_A = 1;
DevCfgRegs.CPUSEL11.bit.ADC_B = 1;
DevCfgRegs.CPUSEL11.bit.ADC_C = 1;
DevCfgRegs.CPUSEL11.bit.ADC_D = 1;
//DevCfgRegs.CPUSEL12.bit.CMPSS1 = 1;
DevCfgRegs.CPUSEL0.bit.EPWM1 = 1;
EDIS;
initCMPSS();
IPCLtoRFlagSet(IPC_FLAG10);
while(0)
{
if (IPCLtoRFlagBusy(IPC_FLAG10)==0)
{
escribirdato();
}
}
}
void cpuTimer0ISR(void){}
void initCputimer(uint32_t jeje){}
void configCputimer(uint32_t cpuTimer,float freq,float period){}
void escribirdato()
{
GPIO_togglePin(DEVICE_GPIO_PIN_LED2);
}
void initCMPSS(void)
{
//
// Enable CMPSS and configure the negative input signal to come from
// the DAC
//
CMPSS_enableModule(CMPSS1_BASE);
CMPSS_configHighComparator(CMPSS1_BASE, CMPSS_INSRC_DAC);
//
// Use VDDA as the reference for the DAC and set DAC value to midpoint for
// arbitrary reference.
//
CMPSS_configDAC(CMPSS1_BASE, CMPSS_DACREF_VDDA | CMPSS_DACVAL_SYSCLK |
CMPSS_DACSRC_SHDW);
CMPSS_setDACValueHigh(CMPSS1_BASE, 2048);
//
// Configure the output signals. Both CTRIPH and CTRIPOUTH will be fed by
// the asynchronous comparator output.
//
CMPSS_configOutputsHigh(CMPSS1_BASE, CMPSS_TRIP_ASYNC_COMP |
CMPSS_TRIPOUT_ASYNC_COMP);
//
// Setup the Output X-BAR to output CTRIPOUTH on OUTPUTXBAR3
//
XBAR_setOutputMuxConfig(XBAR_OUTPUT3, XBAR_OUT_MUX00_CMPSS1_CTRIPOUTH);
XBAR_enableOutputMux(XBAR_OUTPUT3, XBAR_MUX00);
}
CPU2:
// Include
#include "driverlib.h"
#include "device.h"
#include "F2837xD_Ipc_drivers.h"
// Variables Globales
#define BUFFER 256
uint16_t Cpu2Write[256];
uint16_t Cpu2WRead[256];
uint16_t Cpu2ADCC[256];
uint16_t Cpu2ADCD[256];
uint16_t actual=0;
//Se mapea GS1 de la RAM a CPU02 y GS0 de la RAM a CPU1
#pragma DATA_SECTION(Cpu2Write,"SHARERAMGS1");
#pragma DATA_SECTION(Cpu2WRead,"SHARERAMGS0");
#pragma DATA_SECTION(Cpu2ADCC,"SHARERAMGS2");
#pragma DATA_SECTION(Cpu2ADCD,"SHARERAMGS3");
#pragma DATA_SECTION(actual,"SHARERAMGS4");
extern uint16_t isrfuncLoadStart;
extern uint16_t isrfuncLoadEnd;
extern uint16_t isrfuncRunStart;
extern uint16_t isrfuncLoadSize;
//Prototipos de funcion
void InitTimer(uint32_t);
void configTimer(uint32_t,float,float);
__interrupt void Cputimer0(void);
#pragma CODE_SECTION(Cputimer0,"isrfunc")
void Escribirdato(void);
void InitADCs(void);
void InitADCSOCs(void);
void initEPWM(void);
/**
* main.c
*/
int main(void)
{
// Inicializamos PIE y limpiamos el registro PIE
Interrupt_initModule();
// Inicializamos el vector PIE
Interrupt_initVectorTable();
//Espera a que se habilite la RAM compartida
while((HWREGH(MEMCFG_BASE + MEMCFG_O_GSXMSEL) &
(MEMCFG_GSXMSEL_MSEL_GS14 | MEMCFG_GSXMSEL_MSEL_GS15)) == 0U)
{
}
//Copia el ISR en una localizacion especifica de la RAM
memcpy(&isrfuncRunStart,&isrfuncLoadStart, (uint32_t)&isrfuncLoadSize);
Interrupt_register(INT_TIMER0, &Cputimer0);
//Configuracion del timer
InitTimer(CPUTIMER0_BASE);
configTimer(CPUTIMER0_BASE, DEVICE_SYSCLK_FREQ, 1000);
CPUTimer_startTimer(CPUTIMER0_BASE);
//Habilitar la interrupcion del timer0
Interrupt_enable(INT_TIMER0);
//Configuracion del ADC
InitADCs();
InitADCSOCs();
initEPWM();
//Habilitar las interrupciones globales
EINT;
ERTM;
while(1)
{
while(ADC_getInterruptStatus(ADCD_BASE, ADC_INT_NUMBER1) == false)
{
}
ADC_clearInterruptStatus(ADCD_BASE, ADC_INT_NUMBER1);
Cpu2Write[actual]= ADC_readResult(ADCARESULT_BASE, ADC_SOC_NUMBER0);
Cpu2WRead[actual]= ADC_readResult(ADCBRESULT_BASE, ADC_SOC_NUMBER0);
Cpu2ADCC[actual]= ADC_readResult(ADCCRESULT_BASE, ADC_SOC_NUMBER0);
Cpu2ADCD[actual]= ADC_readResult(ADCDRESULT_BASE, ADC_SOC_NUMBER0);
actual++;
if (BUFFER <= actual)
{
actual=0;
}
}
}
void InitTimer(uint32_t cpuTimer)
{
CPUTimer_setPeriod(cpuTimer,0xFFFFFFFF);
CPUTimer_setPreScaler(cpuTimer,0);
CPUTimer_stopTimer(cpuTimer);
CPUTimer_reloadTimerCounter(cpuTimer);
}
void configTimer(uint32_t cpuTimer, float freq, float period)
{
uint32_t temp;
//
// Initialize timer period:
//
temp=(uint32_t)(freq / 1000000 * period);
CPUTimer_setPeriod(cpuTimer, temp);
//
// Set pre-scale counter to divide by 1 (SYSCLKOUT):
//
CPUTimer_setPreScaler(cpuTimer, 0);
//
// Initializes timer control register. The timer is stopped, reloaded,
// free run disabled, and interrupt enabled.
//
CPUTimer_stopTimer(cpuTimer);
CPUTimer_reloadTimerCounter(cpuTimer);
CPUTimer_setEmulationMode(cpuTimer,
CPUTIMER_EMULATIONMODE_STOPAFTERNEXTDECREMENT);
CPUTimer_enableInterrupt(cpuTimer);
}
__interrupt void Cputimer0(void)
{
Escribirdato();
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP1);
}
void Escribirdato(void)
{
Cpu2WRead[0]=Cpu2WRead[0]+1;
}
void InitADCs()
{
ADC_setPrescaler(ADCA_BASE,ADC_CLK_DIV_1_0);
ADC_setPrescaler(ADCB_BASE,ADC_CLK_DIV_1_0);
ADC_setPrescaler(ADCC_BASE,ADC_CLK_DIV_1_0);
ADC_setPrescaler(ADCD_BASE,ADC_CLK_DIV_1_0);
ADC_setMode(ADCA_BASE,ADC_RESOLUTION_12BIT,ADC_MODE_SINGLE_ENDED);
ADC_setMode(ADCB_BASE,ADC_RESOLUTION_12BIT,ADC_MODE_SINGLE_ENDED);
ADC_setMode(ADCC_BASE,ADC_RESOLUTION_12BIT,ADC_MODE_SINGLE_ENDED);
ADC_setMode(ADCD_BASE,ADC_RESOLUTION_12BIT,ADC_MODE_SINGLE_ENDED);
ADC_setInterruptPulseMode(ADCA_BASE,ADC_PULSE_END_OF_CONV);
ADC_setInterruptPulseMode(ADCB_BASE,ADC_PULSE_END_OF_CONV);
ADC_setInterruptPulseMode(ADCC_BASE,ADC_PULSE_END_OF_CONV);
ADC_setInterruptPulseMode(ADCD_BASE,ADC_PULSE_END_OF_CONV);
}
void InitADCSOCs()
{
ADC_setupSOC(ADCA_BASE, ADC_SOC_NUMBER0, ADC_TRIGGER_EPWM1_SOCA,
ADC_CH_ADCIN0, 15);
ADC_setupSOC(ADCA_BASE, ADC_SOC_NUMBER1, ADC_TRIGGER_EPWM1_SOCA,
ADC_CH_ADCIN1, 15);
ADC_setInterruptSource(ADCA_BASE, ADC_INT_NUMBER1, ADC_SOC_NUMBER1);
ADC_enableInterrupt(ADCA_BASE, ADC_INT_NUMBER1);
ADC_clearInterruptStatus(ADCA_BASE, ADC_INT_NUMBER1);
ADC_setupSOC(ADCB_BASE, ADC_SOC_NUMBER0, ADC_TRIGGER_EPWM1_SOCA,
ADC_CH_ADCIN0, 15);
ADC_setupSOC(ADCB_BASE, ADC_SOC_NUMBER1, ADC_TRIGGER_EPWM1_SOCA,
ADC_CH_ADCIN1, 15);
ADC_setInterruptSource(ADCB_BASE, ADC_INT_NUMBER1, ADC_SOC_NUMBER1);
ADC_enableInterrupt(ADCB_BASE, ADC_INT_NUMBER1);
ADC_clearInterruptStatus(ADCB_BASE, ADC_INT_NUMBER1);
ADC_setupSOC(ADCC_BASE, ADC_SOC_NUMBER0, ADC_TRIGGER_EPWM1_SOCA,
ADC_CH_ADCIN0, 15);
ADC_setupSOC(ADCC_BASE, ADC_SOC_NUMBER1, ADC_TRIGGER_EPWM1_SOCA,
ADC_CH_ADCIN1, 15);
ADC_setInterruptSource(ADCC_BASE, ADC_INT_NUMBER1, ADC_SOC_NUMBER1);
ADC_enableInterrupt(ADCC_BASE, ADC_INT_NUMBER1);
ADC_clearInterruptStatus(ADCC_BASE, ADC_INT_NUMBER1);
ADC_setupSOC(ADCD_BASE, ADC_SOC_NUMBER0, ADC_TRIGGER_EPWM1_SOCA,
ADC_CH_ADCIN0, 15);
ADC_setupSOC(ADCD_BASE, ADC_SOC_NUMBER1, ADC_TRIGGER_EPWM1_SOCA,
ADC_CH_ADCIN1, 15);
ADC_setInterruptSource(ADCD_BASE, ADC_INT_NUMBER1, ADC_SOC_NUMBER1);
ADC_enableInterrupt(ADCD_BASE, ADC_INT_NUMBER1);
ADC_clearInterruptStatus(ADCD_BASE, ADC_INT_NUMBER1);
}
void initEPWM(void)
{
//
// Disable the ePWM time base clock before configuring the module
//
SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);
//Disable SOCA/B/C/D
EPWM_disableADCTrigger(EPWM1_BASE,EPWM_SOC_A);
EPWM_disableADCTrigger(EPWM1_BASE,EPWM_SOC_B);
EPWM_setADCTriggerSource(EPWM1_BASE, EPWM_SOC_A, EPWM_SOC_TBCTR_U_CMPA);
EPWM_setADCTriggerEventPrescale(EPWM1_BASE, EPWM_SOC_A, 1);
// Set the time base clock prescalers to /1
//
EPWM_setClockPrescaler(EPWM8_BASE, EPWM_CLOCK_DIVIDER_1,
EPWM_HSCLOCK_DIVIDER_1);
// Initializing dummy values for ePWM counter and period
//
EPWM_setTimeBaseCounter(EPWM8_BASE, 0);
EPWM_setTimeBasePeriod(EPWM8_BASE, 0xFFFF);
//
// Set-up compare
//
EPWM_setCounterCompareValue(EPWM8_BASE, EPWM_COUNTER_COMPARE_B, 0x8000);
//
// Set actions
//
EPWM_setActionQualifierAction(EPWM8_BASE,
EPWM_AQ_OUTPUT_B,
EPWM_AQ_OUTPUT_HIGH,
EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);
EPWM_setActionQualifierAction(EPWM8_BASE,
EPWM_AQ_OUTPUT_B,
EPWM_AQ_OUTPUT_LOW,
EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
//
// Configure ePWM8B to output high on TZB TRIP
//
EPWM_setTripZoneAction(EPWM8_BASE, EPWM_TZ_ACTION_EVENT_TZB,
EPWM_TZ_ACTION_HIGH);
//
// Trigger event when DCBH is high
//
EPWM_setTripZoneDigitalCompareEventCondition(EPWM8_BASE,
EPWM_TZ_DC_OUTPUT_B1,
EPWM_TZ_EVENT_DCXH_HIGH);
//
// Configure DCBH to use TRIP4 as an input
//
EPWM_enableDigitalCompareTripCombinationInput(EPWM8_BASE,
EPWM_DC_COMBINATIONAL_TRIPIN4,
EPWM_DC_TYPE_DCBH);
//
// Enable DCB as OST
//
EPWM_enableTripZoneSignals(EPWM8_BASE, EPWM_TZ_SIGNAL_DCBEVT1);
//
// Configure the DCB path to be unfiltered and asynchronous
//
EPWM_setDigitalCompareEventSource(EPWM8_BASE,
EPWM_DC_MODULE_B,
EPWM_DC_EVENT_1,
EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL);
//
// Sync the ePWM time base clock
//
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);
//
// Configure TRIP4 to be CTRIP1H using the ePWM X-BAR
//
XBAR_setEPWMMuxConfig(XBAR_TRIP4, XBAR_EPWM_MUX00_CMPSS1_CTRIPH);
XBAR_enableEPWMMux(XBAR_TRIP4, XBAR_MUX00);
//
// Clear trip flags
//
EPWM_clearTripZoneFlag(EPWM8_BASE, EPWM_TZ_INTERRUPT |
EPWM_TZ_FLAG_OST);
//
// Put the time base counter into up-count mode
//
EPWM_setTimeBaseCounterMode(EPWM8_BASE, EPWM_COUNTER_MODE_UP);
}
