TMS320F28379D: index pulse does not reset count

don morgan

I thought I had this solved last night but guess not.

The problem is that I can see the index pulse going to the eQEPi pin on the micro. I am using eQEP2 and the quadrature count and A/Ds are producing what look like correct results.

But I can't get the index pulse that I can clearly see on the scope at the eQEPi pin to clear the position count.

I am not using the strobe.

And the SWI (software) clear works.

(this morning) I have now been through the technical reference twice trying every setting I can find on the eQEP to get that count to clear with NO result unless I use SWI.

What am I missing?

Thanks,

Don

over 5 years ago

0 don morgan over 5 years ago

Intellectual 850 points

Something to go with the above--

I find that if I set and reset QIP on the next index event, it does reset the count. To get it to do it again, I have set and reset QIP again.

Does that jar any thoughts?

Thanks,

Don

0 Nirav Ginwala over 5 years ago in reply to don morgan

TI__Genius 15385 points

Hi Don,

Which GPIO pin are you using for Index Pulse?

What board are you using? Is it a custom board or using TI Launcpad?

Regards,

Nirav

0 don morgan over 5 years ago in reply to Nirav Ginwala

Intellectual 850 points

it is the IDDK motor drive development kit.

I took the software from the launchxl and changed the IO pins to conform to the IDDK schematic.

I am using GPIO59 from CMPSS8 to GPIO57 on eQEP2i

This is the init:

// Configure GPIOs as OUTPUTXBARs so that CTRIPHOUTH can be output from chip GPIO14,15,59:
GPIO_SetupPinMux(14, GPIO_MUX_CPU1, 6); //OUTPUTXBAR3 - A
GPIO_SetupPinMux(15, GPIO_MUX_CPU1, 6); //OUTPUTXBAR4 - B
GPIO_SetupPinMux(59, GPIO_MUX_CPU1, 5); //OUTPUTXBAR2 - R

// configure GPIOs 10 & 11 for QEP input
/* EALLOW;
GpioCtrlRegs.GPAGMUX1.bit.GPIO10 = 1; //20, 21 & 23
GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 1;
GpioCtrlRegs.GPAGMUX1.bit.GPIO11 = 1;
GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 1;
GpioCtrlRegs.GPAGMUX1.bit.GPIO13 = 1;
GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 1; */

// configure GPIOs 10 & 11 for QEP input
/* EALLOW;
GpioCtrlRegs.GPAGMUX2.bit.GPIO20 = 1; //20, 21 & 23
GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 1;
GpioCtrlRegs.GPAGMUX2.bit.GPIO21 = 1;
GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 1;
GpioCtrlRegs.GPAGMUX2.bit.GPIO23 = 1;
GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 1; */

// configure GPIOs 54 & 55 for QEP input
EALLOW;
GpioCtrlRegs.GPBGMUX2.bit.GPIO54 = 1; // QEP2-A
GpioCtrlRegs.GPBGMUX2.bit.GPIO55 = 1; // QEP2-B
GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 1; // QEP2-I
GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 1;
GpioCtrlRegs.GPBMUX2.bit.GPIO55 = 1;
GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 1;

GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 2; // Glitchfilter for QEP A
GpioCtrlRegs.GPBQSEL2.bit.GPIO55 = 2; // Glitchfilter for QEP B
GpioCtrlRegs.GPBQSEL2.bit.GPIO56 = 2; // Glitchfilter for QEP S
GpioCtrlRegs.GPBQSEL2.bit.GPIO57 = 2; // Glitchfilter for QEP I
GpioCtrlRegs.GPBCTRL.bit.QUALPRD3 = 3; // Qualification period

/* // configure GPIOs 10 & 11 for QEP input
EALLOW;
GpioCtrlRegs.GPAGMUX1.bit.GPIO10 = 1; //20, 21 & 23
GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 1;
GpioCtrlRegs.GPAGMUX1.bit.GPIO11 = 1;
GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 1;
GpioCtrlRegs.GPAGMUX1.bit.GPIO13 = 1; */

// configure GPIOs 20 & 21 for QEP input
// EALLOW;
// GpioCtrlRegs.GPAGMUX2.bit.GPIO20 = 1; //20, 21 & 23
// GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 1;
// GpioCtrlRegs.GPAGMUX2.bit.GPIO21 = 1;
// GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 1;
// GpioCtrlRegs.GPAGMUX2.bit.GPIO23 = 1;
// GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 1;

/* GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 1; // GPIO qualification for QEP inputs //20, 21 & 23
GpioCtrlRegs.GPAQSEL1.bit.GPIO10 = 2;
GpioCtrlRegs.GPAQSEL1.bit.GPIO11 = 2;
GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 2;
GpioCtrlRegs.GPACTRL.bit.QUALPRD1 = 3; */

// GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 1; // GPIO qualification for QEP inputs //20, 21 & 23
/* GpioCtrlRegs.GPAQSEL2.bit.GPIO20 = 2;
GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 2;
GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 2;
GpioCtrlRegs.GPACTRL.bit.QUALPRD2 = 3;
*/
// initialize PWM
EPwm1Regs.ETSEL.bit.SOCAEN = 1; // enable SOC on A group
EPwm1Regs.ETSEL.bit.SOCASEL = 4; // select SOC on CMPA up-count match
EPwm1Regs.ETSEL.bit.INTEN = 1; // enable interrupt generation
EPwm1Regs.ETSEL.bit.INTSEL = 6; // interrupt on CMPB in up-count mode
EPwm1Regs.ETPS.bit.INTPRD = 1; // generate interrupt on 1st event
EPwm1Regs.ETPS.bit.SOCAPRD = 1; // generate SOC on 1st event
EPwm1Regs.TBPRD = SINCOS_INT_PRD; // set PWM period
EPwm1Regs.CMPA.bit.CMPA = (SINCOS_INT_PRD / 2); // set compare A value to 50% duty [0x0C35]
EPwm1Regs.CMPB.bit.CMPB = (SINCOS_INT_PRD / 2); // CMPB = CMPA
EPwm1Regs.TBCTL.bit.CTRMODE = 3; // freeze counter
EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0; // TBCLK pre-scaler = /1
EPwm1Regs.TBCTL.bit.FREE_SOFT = 3; // free run on emulation suspend
EPwm1Regs.AQCTLA.bit.CAU = 2; // high on compare A match
EPwm1Regs.AQCTLA.bit.PRD = 1; // low on period match

// enable ADCs
AdcSetMode(ADC_ADCA, ADC_RESOLUTION_16BIT, ADC_SIGNALMODE_SINGLE); // 400/2 MHz = 200 MHz
AdcSetMode(ADC_ADCB, ADC_RESOLUTION_16BIT, ADC_SIGNALMODE_SINGLE); // 400/2 MHz = 200 MHz

// configure ADCA
AdcaRegs.ADCCTL2.bit.PRESCALE = 6; // set ADCCCLK divider to /4
AdcaRegs.ADCCTL1.bit.INTPULSEPOS = 0; // ADCAINT1 trips at begin of conversion
AdcaRegs.ADCINTSEL1N2.bit.INT1E = 0; // disable ADCAINT1
AdcaRegs.ADCINTSEL1N2.bit.INT1CONT = 0; // disable ADCAINT1 continuous mode
AdcaRegs.ADCINTSEL1N2.bit.INT1SEL = 0; // disable EOC0 trigger ADCAINT1

// configure ADCB
AdcbRegs.ADCCTL2.bit.PRESCALE = 6; // set ADCDCLK divider to /4
AdcbRegs.ADCCTL1.bit.INTPULSEPOS = 0; // ADCBINT1 trips at begin of conversion
AdcbRegs.ADCINTSEL1N2.bit.INT1E = 1; // enable ADCBINT1
AdcbRegs.ADCINTSEL1N2.bit.INT1CONT = 0; // disable ADCBINT1 continuous mode
AdcbRegs.ADCINTSEL1N2.bit.INT1SEL = 1; // enable EOC1 to trigger ADCBINT1

// sincos channel 0 = ADCA SOC0
AdcaRegs.ADCSOC0CTL.bit.CHSEL = 14; // set SOC0 channel select to ADCIN14
AdcaRegs.ADCSOC0CTL.bit.TRIGSEL = 5; // set SOC0 start trigger on EPWM1 SOCA
AdcaRegs.ADCSOC0CTL.bit.ACQPS = ADC_AQPS - 1; // set SOC0 S/H Window (SYSCLK cycles plus 1)

// sincos channel 1 = ADCB SOC0
AdcbRegs.ADCSOC0CTL.bit.CHSEL = 2; // set SOC0 channel select to ADCINB2
AdcbRegs.ADCSOC0CTL.bit.TRIGSEL = 5; // set SOC0 start trigger on EPWM1 SOCA
AdcbRegs.ADCSOC0CTL.bit.ACQPS = ADC_AQPS - 1; // set SOC0 S/H Window (SYSCLK cycles plus 1)

// sincos channel 2 = ADCA SOC1
AdcaRegs.ADCSOC1CTL.bit.CHSEL = 2; // set SOC1 channel select to ADCINA2
AdcaRegs.ADCSOC1CTL.bit.TRIGSEL = 5; // set SOC1 start trigger on EPWM1 SOCA
AdcaRegs.ADCSOC1CTL.bit.ACQPS = ADC_AQPS - 1; // set SOC1 S/H Window (SYSCLK cycles plus 1)

// sincos channel 3 = ADCB SOC1
AdcbRegs.ADCSOC1CTL.bit.CHSEL = 5; // set SOC1 channel select to ADCINB5
AdcbRegs.ADCSOC1CTL.bit.TRIGSEL = 5; // set SOC1 start trigger on EPWM1 SOCA
AdcbRegs.ADCSOC1CTL.bit.ACQPS = ADC_AQPS - 1; // set SOC1 S/H Window (SYSCLK cycles plus 1)

// Power up the ADCs
AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1;
AdcbRegs.ADCCTL1.bit.ADCPWDNZ = 1;
DELAY_US(1000);

// configure CMPSS4 for sine input
Cmpss4Regs.COMPCTL.bit.COMPDACE = 1; // Enable CMPSS
Cmpss4Regs.COMPCTL.bit.COMPHSOURCE = 0; // NEG signal comes from DAC
Cmpss4Regs.COMPDACCTL.bit.SELREF = 0; // Use VDDA as the reference for DAC
Cmpss4Regs.COMPDACCTL.bit.SWLOADSEL = 0; // DAC update on SYSCLK
Cmpss4Regs.COMPDACCTL.bit.FREESOFT = 3; // free run on emulation suspend
Cmpss4Regs.DACHVALS.bit.DACVAL = 2048; // set reference threshold DAC to midpoint
Cmpss4Regs.COMPHYSCTL.bit.COMPHYS = 2; // Delay for signal noise
Cmpss4Regs.COMPCTL.bit.CTRIPHSEL = 0; // Asynch output feeds CTRIPH and CTRIPOUTH
Cmpss4Regs.COMPCTL.bit.CTRIPOUTHSEL = 0;

OutputXbarRegs.OUTPUT3MUX0TO15CFG.bit.MUX6 = 0; // Set OUTPUTXBAR3's MUX6 as CMPSS4.CTRIPOUTH
OutputXbarRegs.OUTPUT3MUXENABLE.bit.MUX6 = 1; // Enable MUX6

/* // configure CMPSS3 for cosine input
Cmpss3Regs.COMPCTL.bit.COMPDACE = 1; // Enable CMPSS
Cmpss3Regs.COMPCTL.bit.COMPHSOURCE = 0; // NEG signal comes from DAC
Cmpss3Regs.COMPDACCTL.bit.SELREF = 0; // Use VDDA as the reference for DAC
Cmpss3Regs.COMPDACCTL.bit.SWLOADSEL = 0; // DAC update on SYSCLK
Cmpss3Regs.COMPDACCTL.bit.FREESOFT = 3; // free run on emulation suspend
Cmpss3Regs.DACHVALS.bit.DACVAL = 2048; // set reference threshold DAC to midpoint
Cmpss3Regs.COMPHYSCTL.bit.COMPHYS = 2; // Delay for signal noise
Cmpss3Regs.COMPCTL.bit.CTRIPHSEL = 0; // Asynch output feeds CTRIPH and CTRIPOUTH
Cmpss3Regs.COMPCTL.bit.CTRIPOUTHSEL = 0;

OutputXbarRegs.OUTPUT4MUX0TO15CFG.bit.MUX4 = 0; // Set OUTPUTXBAR4's MUX4 as CMPSS3.CTRIPOUTH
OutputXbarRegs.OUTPUT4MUXENABLE.bit.MUX4 = 1; // Enable MUX4 */

// configure CMPSS7 for cosine input
Cmpss7Regs.COMPCTL.bit.COMPDACE = 1; // Enable CMPSS
Cmpss7Regs.COMPCTL.bit.COMPHSOURCE = 0; // NEG signal comes from DAC
Cmpss7Regs.COMPDACCTL.bit.SELREF = 0; // Use VDDA as the reference for DAC
Cmpss7Regs.COMPDACCTL.bit.SWLOADSEL = 0; // DAC update on SYSCLK
Cmpss7Regs.COMPDACCTL.bit.FREESOFT = 3; // free run on emulation suspend
Cmpss7Regs.DACHVALS.bit.DACVAL = 2048; // set reference threshold DAC to midpoint
Cmpss7Regs.COMPHYSCTL.bit.COMPHYS = 2; // Delay for signal noise
Cmpss7Regs.COMPCTL.bit.CTRIPHSEL = 0; // Asynch output feeds CTRIPH and CTRIPOUTH
Cmpss7Regs.COMPCTL.bit.CTRIPOUTHSEL = 0;

OutputXbarRegs.OUTPUT4MUX0TO15CFG.bit.MUX12 = 0; // Set OUTPUTXBAR4's MUX4 as CMPSS3.CTRIPOUTH
OutputXbarRegs.OUTPUT4MUXENABLE.bit.MUX12 = 1; // Enable MUX4

// configure CMPSS 8 for index pulse input
Cmpss8Regs.COMPCTL.bit.COMPDACE = 1; // Enable CMPSS
Cmpss8Regs.COMPCTL.bit.COMPHSOURCE = 0; // NEG signal comes from DAC
Cmpss8Regs.COMPDACCTL.bit.SELREF = 0; // Use VDDA as the reference for DAC
Cmpss8Regs.DACHVALS.bit.DACVAL = 1024; // Set DAC to midpoint for arbitrary reference [2048]
Cmpss8Regs.COMPHYSCTL.bit.COMPHYS = 2; // Delay for signal noise
Cmpss8Regs.COMPCTL.bit.CTRIPHSEL = 0; // Asynch output feeds CTRIPH and CTRIPOUTH
Cmpss8Regs.COMPCTL.bit.CTRIPOUTHSEL = 0;

OutputXbarRegs.OUTPUT2MUX0TO15CFG.bit.MUX14 = 0; // Set OUTPUTXBAR2's MUX14 as CMPSS1.CTRIPOUTH
OutputXbarRegs.OUTPUT2MUXENABLE.bit.MUX14 = 1; // Enable MUX14

// QEP initialization
mySincos.qep = &EQep2Regs; // assign QEP instance to sincos library

// IPD initialization
for (ch2idx = 0, ch3idx = 0; ch2idx < AVG_FILTER_LENGTH; ch2idx++)
{
ch2arr[ch2idx] = ADC_MAX_RDG >> 1;
ch3arr[ch2idx] = ADC_MAX_RDG >> 1;
}
ch2idx = 0;
ch2sum = 0;
ch3sum = 0;
ch2avg = 0;
ch3avg = 0;

EDIS;
}

Thanks,

Don

0 don morgan over 5 years ago in reply to don morgan

Intellectual 850 points

OK, the reason it didn't respond to the index properly is that I had not correctly mux'd GPIO57. That done, in 12 bit mode everything appears to work very well.

If I move to 16 bit mode, however, it gets all clogged up and fails to run correctly.

Thanks,

Don

0 Nirav Ginwala over 5 years ago in reply to don morgan

TI__Genius 15385 points

Hi Don,

Ok, looks like eQEP index issue is resolved. Let me forward this thread to ADC expert.

Regards,

Nirav

0 Devin Cottier over 5 years ago in reply to Nirav Ginwala

TI__Guru 60865 points

Hi Don,

Sorry for the delay. The differences in 16-bit mode are (1) ADC conversions take longer (2) ADC conversions are in the range 0 to 65535 instead of 0 to 4095 and (3) the input signal is fully differential, which will generally require different signal conditioning circuitry.

For (3) you could switch to the unsupported 12-bit differential mode to see if the signal format is the culprit (conversion time and resolution will be the same). For (1) and (2) you could try the unsupported 16B single-ended mode to check if it is one of the other conditions.

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TMS320F28379D: index pulse does not reset count