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TMS320F280049C: questions to documents

Koichiro Tashiro
Mastermind 22945 points
Part Number: TMS320F280049C


Hi,

I have a several questions from my customer regarding F280049 documents.

Q1)
There are a few differences in memory map in datasheet(table 6-1) and sprt731a.pdf(Figure 1)
Please see below picture and answer these questions.


According to TRM section 3.11.1.2 Local Shared RAM, LSx can be configured as “CLA program RAM”.
In such case,
Q2-1)
At CLA boot-up, program codes in “CLA Program ROM” is loaded(copied) to “CLA Program RAM”, then CLA executes the code from “CLA Program RAM”, correct?
Q2-2)
When CLA is used, “CLA Program RAM” must be used (LSx must be configured as “CLA Program RAM”) ?
Q2-3)
If answer to Q2-2) is “No”, CLA can execute the code directly from “CLA Program ROM”, correct?
And what are differences between using RAM and ROM ? Access latencies?

Q3)
In TRM table3-10, what are exact differences among below terms?
“Emulation Read/Write” vs “Emulation Data Read/Write” vs “Data Read/Write”
“Emulation Program Read/Write” vs “Data Read/Write”

When LSx RAM is shared between CPU and CLA, CPU can freely access to LSx RAM.
Q4-1)
Customer understood it was different in CLA(type-0). In type-0, CPU access is not permitted as default and optionally enabled.
What is the reason TI changed it in Type-2?
Q4-2)
Is there any hardware mechanism to avoid access conflicts between CPU and CLA?
Any software solutions?

Q5)
There are some modules which can be accessed by either CPU or CLA, for example ePWM.
Is there any hardware mechanism to avoid access conflicts between CPU and CLA?
Or software needs to handle them exclusively?

In datasheet table 6-2 CLA Data ROM Memory Map,
Q6-1)
What is difference between “(Load)” and “(Run)”?
Q6-2)
It seems “FFT Table (Run)” address(0xF070 to 0xF86F) overlap with “GS1 RAM”(0xE000 to 0xFFFF) in Table 6-1
How these region relates each other?

Thanks and regards,
Koichiro Tashiro

  • 0
    TI__Guru** 115881 points

    Hi,

    Information in datasheet is correct. Block diagram in datasheet ("Figure 1-1. Functional Block Diagram" ) shows the CLA program ROM and in section "6.3.2 Control Law Accelerator (CLA) ROM Memory Map" it is mentioned that please refer device TRM for information about CLA Program ROM.

     Q2-1)
    At CLA boot-up, program codes in “CLA Program ROM” is loaded(copied) to “CLA Program RAM”, then CLA executes the code from “CLA Program RAM”, correct?

    CLA execution is based on task assigned to it which user need to define. It does not start execution after reset release. Please CLA chapter in TRM for more detail.

     Q2-2)
    When CLA is used, “CLA Program RAM” must be used (LSx must be configured as “CLA Program RAM”) ?

    Correct.

     Q2-3)
    If answer to Q2-2) is “No”, CLA can execute the code directly from “CLA Program ROM”, correct?
    And what are differences between using RAM and ROM ? Access latencies?

    ROMs have predefined code from TI. User can call the function which are in ROM but can not change the code in ROM. They have to put their code in RAM only.

     Q3)
    In TRM table3-10, what are exact differences among below terms?
    “Emulation Read/Write” vs “Emulation Data Read/Write” vs “Data Read/Write”
    “Emulation Program Read/Write” vs “Data Read/Write”

    Emulation read/write meaning read/write via CCS memory watch window where as normal read/write means read/write from CPU code. 

      Q4-1)
    Customer understood it was different in CLA(type-0). In type-0, CPU access is not permitted as default and optionally enabled.
    What is the reason TI changed it in Type-2?

    It is not related to CLA type but bus architecture. Please let me know which device you are referring here. On this device it was done this way so that if customer is not using CLA then they need not to change the setting.

     Q4-2)
    Is there any hardware mechanism to avoid access conflicts between CPU and CLA?
    Any software solutions?

    Define memory as CLA program memory then there is no conflict. Right? 

     Q5)
    There are some modules which can be accessed by either CPU or CLA, for example ePWM.
    Is there any hardware mechanism to avoid access conflicts between CPU and CLA?
    Or software needs to handle them exclusively?

    There is access protection mechanism in hardware which user can enable to block the access from any master. Please refer section "3.14.18 PERIPH_AC_REGS Registers".

     In datasheet table 6-2 CLA Data ROM Memory Map,
    Q6-1)
    What is difference between “(Load)” and “(Run)”?

    I'll check and get back to you.

     Q6-2)
    It seems “FFT Table (Run)” address(0xF070 to 0xF86F) overlap with “GS1 RAM”(0xE000 to 0xFFFF) in Table 6-1
    How these region relates each other?

    I'll check and get back to you.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    TI__Guru** 115881 points

    Hi,

     Q6-1)
    What is difference between “(Load)” and “(Run)”?

    Load is address for C28x CPU view and Run is address for CLA view. 

     Q6-2)
    It seems “FFT Table (Run)” address(0xF070 to 0xF86F) overlap with “GS1 RAM”(0xE000 to 0xFFFF) in Table 6-1
    How these region relates each other?

    [/quote]

    This is correct but as mentioned earlier, Run is address for CLA which does not have access to GS1 RAM so this is really not an overlap for CLA and for C28x CPU the address is different (Load address).

    Hope it is clear. 

    Regards,

    Vivek Singh