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TMS320F28379D: Software triggered interrupts

Ralf Bartling
Expert 1135 points
Part Number: TMS320F28379D

Hello,

I have a question regarding software triggered interrupts.

 In my application I have used INT12 from group 7 to trigger an interrupt. This is an empty slot in the table (see picture).

 

This works fine.

 What happens if one interrupt from the peripheral (in this case the DMA) is issued at the same time when the c28x sets the bit 12 in PIEIFR7?

 Is this interrupt omitted?

 

 

Thank you very much

Ralf

  • 0
    TI__Guru 62975 points

    Ralf,

    The PIE is able to track interrupt status with both Group and Channel granularity.  In the scenario where you trigger an unused INT7.12, the PIE will still be able to monitor the interrupt status of other channels in group 7, for example INT7.3 from DMA.CH3.

    -Tommy

  • 0 in reply to tlee
    Expert 1135 points

    Dear Tommy,

    Thank you very much for your response.

    But what happens if the DMA issues an INT7.3 interrupt exact at the same when the C28x writes back to the PIEIFR7 register and sets the bit 12. The access to the PIEIFR7 is made with an OR instruction. One of your colleagues told me that the OR instruction is an “atomic read modify write” operation.

    In the TRM is written:The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause inadvertent cancellation of other interrupts.

    Can this problem also occur by using the “atomic read modify write” OR operation which is used from the C28x to set bit 12?

    Best regards

    Ralf

  • 0 in reply to Ralf Bartling
    TI__Guru 62975 points

    Ralf,

    Thanks for clarifying your concern.  It looks like there is already a note in the TRM that warns of the scenario that you described:

    -Tommy