TMS320F28379D: How to avoid output signals when starting PWM

Torsten Robitzki

Part Number: TMS320F28379D

Hello,

in the corse of initiating 3 PWMs, I always end up with a signal pattern, that I do not expect. I really appreciate the quality of the reference manual. It's very well written and easy to comprehend. I probably missed something, I did not managed to set the PWM up, so that both A and B stay at low and to have a duty cycle of 0% for the first PWM period (it seems to be close to 100%).

I've initialized the PWM Time Base as Up/Down counter. I configured output A to reset when TBCTR = 0, to switch to high, when TBCTR = CMPA on up counting and to go back to low when TBCTR = CMPB. That work very well. I generate a complementary output B, by configuring the dead band module to generate a RED and FED and to set B to be inverted from A. That works very well too.

But: As soon as I configure the dead band module, the B outputs go to high. I've mitigate that by, forcing a CBC trip zone event, that sets the outputs to low and get reseted at the end of the first period. That reduces the time, the complementary outputs are high to a few ~10ns (one period of the PWMCLK). Is there a way to use the dead band module to generate a complementary output, without setting the B output to 1 immediately or to get rid of the 10ns glitch? (maybe reseting the CBC event at the beginning of the period, not the end)

The "trick" with the trip zone event also has the nice side effect, that the output stay low during the first period.

best regards,

Torsten Robitzki

over 4 years ago

0 Nima Eskandari over 4 years ago

TI__Guru 52040 points

When you get the ePWM outputs to be in complementary mode using the deadband module, the B output will be HIGH if the A output is set to low. That is as expected.

I dont think you need to have the TripZone used for this scenario at all.

Nima

0 Torsten Robitzki over 4 years ago in reply to Nima Eskandari

Expert 2453 points

Hi Nima,

when I omit the TripZone, I get a switch-on behavior that looks like this:

The B outputs switch to high, as soon as I configure the dead band modules (which mean, this could last for unpredictable high times, when interrupts are enabled).

After turning on the TB Clock, the first period outputs a 100% duty cycle. I tried to set both, the compare register and its shadow register to 0 (to no reveal):

        EPWM_disableCounterCompareShadowLoadMode(base, EPWM_COUNTER_COMPARE_A);
        EPWM_setCounterCompareValue(base, EPWM_COUNTER_COMPARE_A, 0);
        EPWM_setCounterCompareShadowLoadMode(base, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO);
        EPWM_setCounterCompareValue(base, EPWM_COUNTER_COMPARE_A, 0);

I would like to configure the PWM, such that I can define the duty cycle of the first period and that none of the outputs start to switch before I start the PWMs all at once (like the wave form of the first post, without the spikes on the B outputs).

regards,

Torsten

0 Nima Eskandari over 4 years ago in reply to Torsten Robitzki

TI__Guru 52040 points

Torsten Robitzki said:
I would like to configure the PWM, such that I can define the duty cycle of the first period and that none of the outputs start to switch before I start the PWMs all at once (like the wave form of the first post, without the spikes on the B outputs).

In that case set up the TRIPZONE Module in oneshot mode, already triggered before enabling the TBCTRs. Once you are ready, clear the TZ ONESHOT event.

0 Torsten Robitzki over 4 years ago in reply to Nima Eskandari

Expert 2453 points

Either, I misunderstood your proposal or it makes it worse. The nice thing about the initial "trick" with a cycle by cycle Tripzone event is, that once the TBCLK is enabled, all Tripzone events are reset on all PWMs without the (maybe unpredictable) delay caused by manually resetting the flags. Attached is a screen shot, where I do not trigger a CBC event (like in the first version above), but a one shot event as you suggest and where I reset the flags (on all three PWMs) before starting the TBCLK (version1) or after starting the TBCLK (version2).

0 Nima Eskandari over 4 years ago in reply to Torsten Robitzki

TI__Guru 52040 points

Why doesnt just enabling the TBCLKSYNC after you have iniailized all your EPWM modules do what you need?

SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);

your issue is that your configuration somehow the first cycle is NOT 100%. I think that is because of event priority most likely.

Either way you can definitley achieve this by doing a TRUE 100% duty, or use DCBEVT and use a SW force to make sure that is low for the first cycle. then clear the DCBEVT at TBCTR=PRD.

Nima

0 Torsten Robitzki over 4 years ago in reply to Nima Eskandari

Expert 2453 points

> Why doesnt just enabling the TBCLKSYNC after you have iniailized all your EPWM modules do what you need?

Well, that is what I've meant, when I wrote "After turning on the TB Clock" or "once the TBCLK is enabled". Try it on your own: Disable TBCLKSYNC configure the PWMs. You will observe, that as soon as you start to configure your B outputs to be the complementary output to A, using the the Dead Band module, the B outputs become active high (the screen shot from the 15th of Sept.). You can mitigate that by manually triggering a CBC Tripzone event and then enabling the TBCLKSYNC. This results in a delay of one period and 10ns (likely depends on the PWM clock frequency) spikes at the beginning (first screenshot).

Anyway, I think we can live with the initial workaround. Thank you for the time you've spend on this.

regards,

Torsten

0 Nima Eskandari over 4 years ago in reply to Torsten Robitzki

TI__Guru 52040 points

You are correct I also observed this. If I find a work around I will post it on here later. Thank you for reporting this.

Nima

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TMS320F28379D: How to avoid output signals when starting PWM