28335 ADC

Gajanan,

ADC INT is legacy from a previous device; it is logical OR of SEQ1 and SEQ2 interrupts.  If you are in cascaded mode only SEQ1 will be triggered.  However, using MAXCONV you can set this up so that SEQ1 would be triggered at different points during the cascaded mode.

Best,

Matthew

Matthew,

Thanks for your reply.  Does it mean that for cascaded mode, it will generate both SEQ1 and SEQ2 interrupts? I thought that it will generate SEQ1 and SEQ2 for independent conversions, and for cascaded mode it will generate ADC INT.

If they are logical ORed then it will generate all three interrputs (SEQ1, SEQ2 and ADC INT) for cascaded mode ?

Gajanan

MatthewPate said:

Gajanan,

ADC INT is legacy from a previous device; it is logical OR of SEQ1 and SEQ2 interrupts.  If you are in cascaded mode only SEQ1 will be triggered.  However, using MAXCONV you can set this up so that SEQ1 would be triggered at different points during the cascaded mode.

Best,

Matthew

Hi, guys,

I have similar problem/question when using F2812 ADC.

The following is my setting:

// *****************************************************************************
// *****************************************************************************
// ADC start parameters
#define ADC_MODCLK  0x05                // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 150MHz/(2*5) = 15MHz
#define ADC_CKPS    0x0A                // ADC module clock = HSPCLK/(2*10) = 15MHz/(20) = 0.75MHz
#define ADC_CPS     0x00                // ADC core clock prescaler, ADC_CLK = 0.75MHz/(0+1) = 0.75MHz
#define ADC_SHCLK   0x01                // S/H width in ADC module periods = (1+1) = 2 ADC cycle

void ADC_Init(void){
    AdcRegs.ADCTRL1.bit.RESET = 1;
    asm(" RPT #10 || NOP");
    InitAdc();                                // For this example, init the ADC

    AdcRegs.ADCTRL1.bit.SUSMOD=3;             // for debug only

    // Specific ADC setup for this example:
    AdcRegs.ADCTRL1.bit.ACQ_PS = ADC_SHCLK;   // Sequential mode: Sample rate   = 1/[(2+ACQ_PS)*ADC clock in ns]
                                              //                     = 1/(3*40ns) =8.3MHz
                                              // If Simultaneous mode enabled: Sample rate = 1/[(3+ACQ_PS)*ADC clock in ns]
    AdcRegs.ADCTRL1.bit.CPS = ADC_CPS;        // Fclk/2
    AdcRegs.ADCTRL3.bit.ADCCLKPS = ADC_CKPS;  // 750KHz
    AdcRegs.ADCTRL1.bit.SEQ_CASC = 1;         // Cascaded mode
    AdcRegs.ADCTRL1.bit.CONT_RUN = 1;         // Setup continuous run
    AdcRegs.ADCTRL1.bit.SEQ_OVRD = 1;         // Enable Sequencer override feature
    AdcRegs.ADCTRL3.bit.SMODE_SEL=0;          // sequential mode
    AdcRegs.ADCCHSELSEQ1.all = 0x0;           // Initialize all ADC channel selects to A0
    AdcRegs.ADCCHSELSEQ2.all = 0x0;
    AdcRegs.ADCCHSELSEQ3.all = 0x0;
    AdcRegs.ADCCHSELSEQ4.all = 0x0;
    AdcRegs.ADCMAXCONV.bit.MAX_CONV1 = 0x7;   // convert and store in 16 results registers
    AdcRegs.ADCTRL2.bit.INT_MOD_SEQ1 = 0;     // int mode 0
    AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1=1;       // enable int
    AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1;       // Clear INT SEQ1 bit
}

interrupt void ADC_ISR(void){
    // Reinitialize for next ADC sequence
    //AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1;         // Reset SEQ1

    asm(" NOP");asm(" NOP");
    AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1;       // Clear INT SEQ1 bit
    PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;   // Acknowledge interrupt to PIE
}
// *****************************************************************************
// *****************************************************************************

//in main( )

// some configs are omitted

    PieVectTable.ADCINT = &ADC_ISR;
    SysCtrlRegs.HISPCP.all = ADC_MODCLK; // 15MHz
    PieCtrlRegs.PIEIER1.bit.INTx6=1;     // PIE Group 1, INT6, ADC
    IER |= (M_INT1|M_INT9);
    ADC_Init();
    AdcRegs.ADCTRL2.bit.SOC_SEQ1 = 1;       // Start SEQ1
    for(;;);

My problem is, why ADCINT doesn't generate from the above settings?

The following image is the ADC regs when I ran the above settings.

I try to use override, cascade, sequential & continuous, triggered by software, interrupt enabled, single channel - A0 with 16 A0s in ADCRESULTx.

Is it possible that to be configured as, one-shot SW triggered --> interrupt generated when counter decreased to  zero --> reload Maxconv  --> override if  needed -->

--> interrupt generated when counter decreased to zero --> reload Maxconv  --> override if needed .........      continuously and automatically?

Thanks.

Ken.