Compiler/TMS320F28379D: Llinker Cmd file Creation

Rani Loganthan

Intellectual 450 points

Part Number: TMS320F28379D
Other Parts Discussed in Thread: C2000WARE

Tool/software: TI C/C++ Compiler

Hi,

As per application i need to create own Linker cmd file . Creatinga linker command file i have doubt on ,

1. BEGIN has only two address why?

BEGIN : origin = 0x000000, length = 0x000002

over 5 years ago

0 Ozino Odharo over 5 years ago

TI__Mastermind 21305 points

Rani,

I will recommend that you modify an existing linker command file for the f28379xd device for your use application. Please find the example templates in C2000Ware under device_support/f2837xd/common/cmd

For more information on the linker command file please check out this wikipage: https://processors.wiki.ti.com/index.php/C28x_Compiler_-_Understanding_Linking

Regards,

Ozino

0 Rani Loganthan over 5 years ago in reply to Ozino Odharo

Intellectual 450 points

Hi,

I am following the link which you have provided , but i couldnt get clear of why BEGIN has address of two.

Thanks in advance.

Regards,

Rani

0 Vamsi Gudivada over 5 years ago in reply to Rani Loganthan

TI__Guru* 87155 points

Rani,

Once the BROM execution is done, control jumps to flash entry point (0x80000); and BEGIN is used to map the codestart (first code in application that should run after BROM) to this flash entry point location.

In codestart section there will be a branch instruction to c_init routine and this instruction needs 2 locations.

Thanks and regards,
Vamsi

0 Rani Loganthan over 5 years ago in reply to Vamsi Gudivada

Intellectual 450 points

Thanks Vamsi, one more question

1.what is difference between Message RAM(M0), Dedicated RAM(D0) , Local RAM(LS0), Global Shared RAM(GS0)?

2. What is the use of its?Individual needs?

Thanks and Regards,

Rani

0 Vamsi Gudivada over 5 years ago in reply to Rani Loganthan

TI__Guru* 87155 points

Rani,

They all are same type (physically different) of RAM blocks other than the addresses they are mapped to.

In the list of memories that you mentioned:

LSx RAMs are accessibly by CLA while others are not.
GSx RAMs are shared by both CPUs (default owner is CPU1; but they can be configured for CPU2 ownership). These are the only executable (capable of executing code from) RAMs that are shared by both CPUs.
Dx RAMs are accessible only by the respective CPU and are not shared.
Mx RAMs will retain the data even in the Hibernate low power mode where as Dx, LSx, GSx memories does not.

Thanks and regards,
Vamsi

0 Rani Loganthan over 5 years ago in reply to Vamsi Gudivada

Intellectual 450 points

Vamsi,

Thanks for your time ,Your Explanation made that clear to me.

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Compiler/TMS320F28379D: Llinker Cmd file Creation