CCS/TMS320F280049: EPWM4 Phase Shift is not working

Part Number: TMS320F280049

Tool/software: Code Composer Studio

Hello,

i use the same PWM configuration for PWM2,PWM3, PWM4 and the Phase Shift of the PWM4 is not working.

Do you know this issue?

Best regards

Patrick

    EPwm3Regs.TBPRD = SWPERIOD;                             
    EPwm3Regs.TBPHS.bit.TBPHS = 0;                          
    EPwm3Regs.TBCTR = 0;                                   
    EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;          
    EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE;                  
    EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;                  
    EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;              
    EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;                
    EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;                   
    EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;             
    EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;             
    EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD;       
    EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD;       
   
    EPwm3Regs.AQCTLA.bit.CAD = AQ_SET;                     
    EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR;                    
    EPwm3Regs.AQCSFRC.bit.CSFB = AQ_CLEAR;                 

    

    EPwm3Regs.DBCTL.bit.OUT_MODE   = DB_FULL_ENABLE;       
    EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
    EPwm3Regs.DBCTL.bit.IN_MODE = DBA_ALL;
    EPwm3Regs.DBFED.all = 10;                               
    EPwm3Regs.DBRED.all = 10;  

    EPwm3Regs.TZCTL.bit.TZA  = TZ_FORCE_LO;               
    EPwm3Regs.TZCTL.bit.TZB  = TZ_FORCE_LO;               
    EPwm3Regs.TZFRC.bit.OST=1;                            

   
    EPwm4Regs.TBPRD = SWPERIOD;                             
    EPwm4Regs.TBPHS.bit.TBPHS = 0;                          
    EPwm4Regs.TBCTR = 0;                                    
    EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;          
    EPwm4Regs.TBCTL.bit.PHSEN = TB_ENABLE;                 
    EPwm4Regs.TBCTL.bit.PRDLD = TB_SHADOW;                  
    EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;              
    EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;                
    EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV1;                   
    EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;             
    EPwm4Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;             
    EPwm4Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD;       

    EPwm4Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD;       
                 
    EPwm4Regs.AQCTLA.bit.CAD = AQ_SET;                      
    EPwm4Regs.AQCTLA.bit.CAU = AQ_CLEAR;                   
    EPwm4Regs.AQCSFRC.bit.CSFB = AQ_CLEAR;                 

    
    EPwm4Regs.DBCTL.bit.OUT_MODE   = DB_FULL_ENABLE;        
    EPwm4Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
    EPwm4Regs.DBCTL.bit.IN_MODE = DBA_ALL;
    EPwm4Regs.DBFED.all = 10;                               
    EPwm4Regs.DBRED.all = 10;                               
    // Set up Trip Zone regs (TZ)
    //EPwm4Regs.TZSEL.bit.CBC1 = TZ_DISABLE;                  
    //EPwm4Regs.TZSEL.bit.OSHT1 = TZ_ENABLE;                
    EPwm4Regs.TZCTL.bit.TZA  = TZ_FORCE_LO;               
    EPwm4Regs.TZCTL.bit.TZB  = TZ_FORCE_LO;               
    EPwm4Regs.TZFRC.bit.OST=1;                            

    EPwm4Regs.CMPA.bit.CMPA = SWPERIOD/2;                      

   CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;


MAIN:

EALLOW;
//Phase Shift Mode
EPwm2Regs.TBPHS.bit.TBPHS = SWPERIOD*50.0/180.0;
EPwm3Regs.TBPHS.bit.TBPHS = SWPERIOD*50.0/180.0;
EPwm4Regs.TBPHS.bit.TBPHS = SWPERIOD*50.0/180.0;
EDIS;