Tool/software: Code Composer Studio
Hello,
I have found a weird problem when using DCAEVT2 to trigger 2 PWM outputs. When the real value CMPINxP is higher than the max. reference value RAMPMAXREFS, COMPSTS and the corresponding DCAEVT2 are continuously high and then the lagging bridge shoots through. It's weird since Dead Band Submodule use only EPWMA as input to generate two complementary outputs, and the triggering behaviour of T1 is before inserting DB. Therofore theoretically the shoot-through shouldn't show up. Another weird thing is when I also set T1 as the trigger source of EPWMB, one of the outputs became different, even if I had never used EPWMB as the input of DB Submodule.
Thank you very much in advance!
Yutan
EALLOW; EPwm1Regs.TBPRD = (PRD_cal >> 9); EPwm1Regs.TBPRDHR = ((PRD_cal & 0x7f))<<8; EPwm1Regs.TBPHS.all = 0; EPwm1Regs.TBCTL.bit.FREE_SOFT = 0b11; EPwm1Regs.TBCTL.bit.PHSDIR = 1;//up after syn EPwm1Regs.TBCTL.bit.CLKDIV = 0; EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0;//no divide EPwm1Regs.TBCTL.bit.SYNCOSEL = 1;//syn out = CMPC EPwm1Regs.TBCTL2.bit.SYNCOSELX= 1; EPwm1Regs.CMPC = (PRD_cal >> 8)-2; EPwm1Regs.TBCTL.bit.PRDLD = 0;//shadow mode EPwm1Regs.TBCTL.bit.PHSEN = 0;//epwmno is master EPwm1Regs.TBCTL.bit.CTRMODE = 2;//up down count EPwm1Regs.CMPCTL.bit.SHDWAMODE= 0;//shadow mode EPwm1Regs.CMPCTL.bit.LOADAMODE= 0;//load at CTR=ZRO duty_cal = (Uint32)(PRD_cal * 0.5); EPwm1Regs.CMPA.bit.CMPA = duty_cal >> 8; EPwm1Regs.CMPA.bit.CMPAHR = (duty_cal & 0xff)<<8; EPwm1Regs.AQCTLA.bit.PRD = 0b01; EPwm1Regs.AQCTLA.bit.ZRO = 0b10;//ZRO is set EPwm1Regs.AQSFRC.bit.RLDCSF = 0b01; EPwm1Regs.HRCNFG.all = 0; EPwm1Regs.HRCNFG.bit.HRLOAD = 0;//load at PRD EPwm1Regs.HRCNFG.bit.CTLMODE = 0;//phase control mode EPwm1Regs.HRCNFG.bit.EDGMODE = 3;//both edges EPwm1Regs.HRCNFG.bit.HRLOADB = 0;//load at PRD EPwm1Regs.HRCNFG.bit.CTLMODEB = 0;//phase control mode EPwm1Regs.HRCNFG.bit.EDGMODEB = 3;//both edges EPwm1Regs.HRCNFG.bit.AUTOCONV = 1;//auto scaling is enable EPwm1Regs.HRPCTL.bit.TBPHSHRLOADE = 1; EPwm1Regs.HRPCTL.bit.HRPE = 1;//HRPRD is enable EPwm1Regs.DBCTL.bit.HALFCYCLE = 0;//enable half cycle EPwm1Regs.DBCTL.bit.SHDWDBFEDMODE = 1; EPwm1Regs.DBCTL.bit.SHDWDBREDMODE = 1; EPwm1Regs.DBCTL.bit.POLSEL = 0b10;//AHC EPwm1Regs.DBCTL.bit.OUT_MODE = 0b11;//AHC deadtime_cal = target->PWM_DRV_OBJ_P_INS->dbtime * 256 / 5; EPwm1Regs.DBFED.bit.DBFED = deadtime_cal >> 8; EPwm1Regs.DBRED.bit.DBRED = deadtime_cal >> 8; EPwm1Regs.DBFEDHR.bit.DBFEDHR = deadtime_cal & 0xff; EPwm1Regs.DBREDHR.bit.DBREDHR = deadtime_cal & 0xff; EPwm1Regs.HRCNFG2.bit.CTLMODEDBFED = 0; EPwm1Regs.HRCNFG2.bit.CTLMODEDBRED = 0; EPwm1Regs.HRCNFG2.bit.EDGMODEDB = 0b11; EPwm2Regs.TBCTL.bit.FREE_SOFT = 0b10; EPwm2Regs.TBCTL.bit.PHSDIR = 1;//up after syn EPwm2Regs.TBCTL.bit.CLKDIV = 0; EPwm2Regs.TBCTL.bit.HSPCLKDIV = 0;//no divide EPwm2Regs.TBCTL.bit.SYNCOSEL = 0;//syn out when CTR=0 EPwm2Regs.TBCTL.bit.PRDLD = 0;//shadow mode EPwm2Regs.TBCTL.bit.PHSEN = 1;//epwmno+1 is slaver EPwm2Regs.TBCTL.bit.CTRMODE = 2;//up down count EPwm2Regs.TBPRD = (PRD_cal >> 9); EPwm2Regs.TBPRDHR = (PRD_cal & 0x7f)<<8; EPwm2Regs.AQCTLA.bit.ZRO = 0b10;//ZRO is set EPwm2Regs.AQCTLA.bit.PRD = 0b01;//PRD is clr EPwm2Regs.AQCTLA2.bit.T1U = 0b01;//T1 up is clr EPwm2Regs.AQCTLA2.bit.T1D = 0b10;//T1 down is set EPwm2Regs.AQTSRCSEL.bit.T1SEL = 0b1000; EPwm2Regs.AQSFRC.bit.RLDCSF = 0b01; EPwm2Regs.TBPHS.bit.TBPHS = 0; EPwm2Regs.TRREM.bit.TRREM = 0; EPwm2Regs.HRCNFG.all = 0; EPwm2Regs.HRCNFG.bit.HRLOAD = 0;//load at PRD EPwm2Regs.HRCNFG.bit.CTLMODE = 1;//phase control mode EPwm2Regs.HRCNFG.bit.EDGMODE = 3;//both edges EPwm2Regs.HRCNFG.bit.HRLOADB = 0;//load at PRD EPwm2Regs.HRCNFG.bit.CTLMODEB = 1;//phase control mode EPwm2Regs.HRCNFG.bit.EDGMODEB = 3;//both edges EPwm2Regs.HRCNFG.bit.AUTOCONV = 1;//auto scaling is enable EPwm2Regs.HRPCTL.bit.TBPHSHRLOADE = 1; EPwm2Regs.HRPCTL.bit.HRPE = 1;//HRPRD is enable EPwm2Regs.DBCTL.bit.IN_MODE = 0b00; EPwm2Regs.DBCTL.bit.DEDB_MODE = 0; EPwm2Regs.DBCTL.bit.HALFCYCLE = 1;//enable half cycle EPwm2Regs.DBCTL.bit.SHDWDBFEDMODE = 1; EPwm2Regs.DBCTL.bit.SHDWDBREDMODE = 1; EPwm2Regs.DBCTL.bit.POLSEL = 0b10;//AHC EPwm2Regs.DBCTL.bit.OUT_MODE = 0b11;//AHC EPwm2Regs.DBCTL.bit.OUTSWAP = 0b11; EPwm2Regs.DBFED.bit.DBFED = deadtime_cal >> 8; EPwm2Regs.DBRED.bit.DBRED = deadtime_cal >> 8; EPwm2Regs.DBFEDHR.bit.DBFEDHR = deadtime_cal & 0xff; EPwm2Regs.DBREDHR.bit.DBREDHR = deadtime_cal & 0xff; EPwm2Regs.HRCNFG2.bit.CTLMODEDBFED = 0; EPwm2Regs.HRCNFG2.bit.CTLMODEDBRED = 0; EPwm2Regs.HRCNFG2.bit.EDGMODEDB = 0b11; //PWM+2 EPwm3Regs.TBCTL.bit.FREE_SOFT = 0b10; EPwm3Regs.TBCTL.bit.PHSDIR = 1;//up after syn EPwm3Regs.TBCTL.bit.CLKDIV = 0; EPwm3Regs.TBCTL.bit.HSPCLKDIV = 0;//no divide EPwm3Regs.TBCTL.bit.SYNCOSEL = 0;//syn out when CTR=0 EPwm3Regs.TBCTL.bit.PRDLD = 0;//shadow mode EPwm3Regs.TBCTL.bit.PHSEN = 1;//epwmno+1 is slaver EPwm3Regs.TBCTL.bit.CTRMODE = 0;//up count EPwm3Regs.TBPRD = (PRD_cal >> 9)-1; EPwm3Regs.TBPHS.bit.TBPHS = 0; EPwm3Regs.TRREM.bit.TRREM = 0; EPwm3Regs.HRPCTL.bit.PWMSYNCSEL = 1; // PWM + 1 as pcmc (*(volatile Uint32*)(0x7A00+0x20)) = (1<<(2*(target->CMPSS_PCMC_OBJ_P_INS->port))); EPwm2Regs.DCFCTL.bit.PULSESEL = 2;//Blanking for both CTR = 0 and CTR = PRD EPwm2Regs.DCFCTL.bit.BLANKE = 1;//Blanking Enable // EPwm2Regs.DCFCTL.bit.BLANKE = 0; EPwm2Regs.DCFCTL.bit.SRCSEL = 0b01; EPwm2Regs.DCFWINDOW = target->PWM_DRV_OBJ_P_INS->blankwin; EPwm2Regs.DCTRIPSEL.bit.DCAHCOMPSEL = 0b0011;//DCAH Trip Select: 0011 = TRIPIN4 EPwm2Regs.DCACTL.bit.EVT2SRCSEL= 1;//DCAEVT2 Source Signal Select: 1= DCEVTFILT Signal, 0 = DCAEVT2; EPwm2Regs.DCACTL.bit.EVT2FRCSYNCSEL = 1;//FRC Synchro EPwm2Regs.TZDCSEL.bit.DCAEVT2 = 0b010;//DCAH high EDIS;
