Part Number: TMS320F28035
Dear team:
One of my clients has upgraded the chip online through SCI port, and can complete the jump from boot layer to app layer. The main CPU runs correctly, but the CLA core cannot run.
I guess the problem may be in the configuration of the CMD file. That is, boot layer and app layer flash and ram division.
Bootloader code is divided on FlashA, APP code is divided on flashH~flashD, and other ram is not changed greatly. The following is the contents of the boot layer's cmd file:
CLA_SCRATCHPAD_SIZE = 0x100;
--undef_sym=__cla_scratchpad_end
--undef_sym=__cla_scratchpad_start
_Cla1Prog_Start = _Cla1funcsRunStart;
-heap 0x100
-m UltraSonicPower200.map
MEMORY
{
PAGE 0: /* Program Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
RAMLISR_PRG : origin = 0x008000, length = 0x000100 /* on-chip RAM block L0 */
RAMLAPP_PRG : origin = 0x008100, length = 0x000400 /* on-chip RAM block L0 */
//RAMLBOOT_PRG : origin = 0x008400, length = 0x000100 /* on-chip RAM block L0 */
//RAML1 : origin = 0x008800, length = 0x000400 /* on-chip RAM block L1 */
RAML3 : origin = 0x009000, length = 0x001000 /* on-chip RAM block L3, for CLA run code */
OTP : origin = 0x3D7800, length = 0x000400 /* on-chip OTP */
FLASHH : origin = 0x3e8000, length = 0x00A000 /* on-chip FLASH */
//FLASHH : origin = 0x3E8000, length = 0x002000 /* on-chip FLASH */
//FLASHG : origin = 0x3EA000, length = 0x002000 /* on-chip FLASH */
//FLASHF : origin = 0x3EC000, length = 0x002000 /* on-chip FLASH */
//FLASHE : origin = 0x3EE000, length = 0x002000 /* on-chip FLASH */
//FLASHD : origin = 0x3F0000, length = 0x002000 /* on-chip FLASH */
FLASHC : origin = 0x3F2000, length = 0x002000 /* on-chip FLASH */
FLASHA : origin = 0x3F6000, length = 0x001F80 /* on-chip FLASH */
CSM_RSVD : origin = 0x3F7F80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
BEGIN : origin = 0x3F7FF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */
CSM_PWL_P0 : origin = 0x3F7FF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
IQTABLES : origin = 0x3FE000, length = 0x000B50 /* IQ Math Tables in Boot ROM */
IQTABLES2 : origin = 0x3FEB50, length = 0x00008C /* IQ Math Tables in Boot ROM */
IQTABLES3 : origin = 0x3FEBDC, length = 0x0000AA /* IQ Math Tables in Boot ROM */
ROM : origin = 0x3FF27C, length = 0x000D44 /* Boot ROM */
RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */
VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */
PAGE 1 : /* Data Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
/* Registers remain on PAGE1 */
BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */
RAMM0 : origin = 0x000080, length = 0x0007B0 /* on-chip RAM block M0, and M1 is incorporated to M0 */
// RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
DataRAM : origin = 0x008500, length = 0x0006FF /*on-chip RAM block L0,L1 */
BootFlagRAM : origin = 0x008BFF, length = 0x000001 /* on-chip RAM block L1 */
CLARAM1 : origin = 0x008C00, length = 0x000400 /* on-chip RAM block L2 */
//RAML3 : origin = 0x009000, length = 0x001000 /* on-chip RAM block L3 */
CLA1_MSGRAMLOW : origin = 0x001480, length = 0x000080
CLA1_MSGRAMHIGH : origin = 0x001500, length = 0x000080
FLASHB : origin = 0x3F4000, length = 0x002000 /* on-chip FLASH */
}
SECTIONS
{
/* Allocate program areas: */
.cinit : > FLASHA PAGE = 0
.pinit : > FLASHA, PAGE = 0
.text : > FLASHA PAGE = 0
codestart : > BEGIN PAGE = 0
IsrRamfuncs : LOAD = FLASHA,
RUN = RAMLISR_PRG,
LOAD_START(_IsrRamfuncsLoadStart),
LOAD_END(_IsrRamfuncsLoadEnd),
RUN_START(_IsrRamfuncsRunStart),
PAGE = 0
ramfuncs : LOAD = FLASHA,
RUN = RAMLAPP_PRG,
LOAD_START(_RamfuncsLoadStart),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
PAGE = 0
csmpasswds : > CSM_PWL_P0 PAGE = 0
csm_rsvd : > CSM_RSVD PAGE = 0
debug_ram : > DataRAM PAGE = 1
BootFlagRam : > BootFlagRAM PAGE = 1
/* Allocate uninitalized data sections: */
//.stack : > RAMM0 PAGE = 1
.stack : > DataRAM PAGE = 1
.ebss : > RAMM0 PAGE = 1
// .esysmem : > RAMM0 PAGE = 1
//.sysmem : > RAMM0 PAGE = 1
/* Initalized sections go in Flash */
/* For SDFlash to program these, they must be allocated to page 0 */
.econst : > FLASHA PAGE = 0
.switch : > FLASHA PAGE = 0
/* Allocate IQ math areas: */
IQmath : > FLASHA PAGE = 0 /* Math Code */
IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD
.bss_cla : > CLARAM1, PAGE = 1
.scratchpad : > CLARAM1, PAGE = 1
Cla1Prog : LOAD = FLASHH,
RUN = RAML3,
LOAD_START(_Cla1funcsLoadStart),
LOAD_END(_Cla1funcsLoadEnd),
RUN_START(_Cla1funcsRunStart),
LOAD_SIZE(_Cla1funcsLoadSize),
PAGE = 0
Cla1ToCpuMsgRAM : > CLA1_MSGRAMLOW, PAGE = 1
CpuToCla1MsgRAM : > CLA1_MSGRAMHIGH, PAGE = 1
// Cla1DataRam0 : > CLARAM0, PAGE = 1
Cla1DataRam1 : > CLARAM1, PAGE = 1
CLA1mathTables : LOAD = FLASHB,
RUN = CLARAM1,
LOAD_START(_Cla1mathTablesLoadStart),
LOAD_END(_Cla1mathTablesLoadEnd),
RUN_START(_Cla1mathTablesRunStart),
LOAD_SIZE(_Cla1mathTablesLoadSize),
PAGE = 1
CLAscratch :
{ *.obj(CLAscratch)
. += CLA_SCRATCHPAD_SIZE;
*.obj(CLAscratch_end) } > CLARAM1,
PAGE = 1
/*
IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
}
/* .reset is a standard section used by the compiler. It contains the */
/* the address of the start of _c_int00 for C Code. /*
/* When using the boot ROM this section and the CPU vector */
/* table is not needed. Thus the default type is set here to */
/* DSECT */
.reset : > RESET, PAGE = 0, TYPE = DSECT
vectors : > VECTORS PAGE = 0, TYPE = DSECT
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
The following is the content of the app layer's CMD file:
CLA_SCRATCHPAD_SIZE = 0x100;
--undef_sym=__cla_scratchpad_end
--undef_sym=__cla_scratchpad_start
_Cla1Prog_Start = _Cla1funcsRunStart;
-heap 0x100
-m UltraSonicPower200.map
MEMORY
{
PAGE 0: /* Program Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
RAMLISR_PRG : origin = 0x008000, length = 0x000100 /* on-chip RAM block L0 */
RAMLAPP_PRG : origin = 0x008100, length = 0x000300 /* on-chip RAM block L0 */
RAMLBOOT_PRG : origin = 0x008400, length = 0x000100 /* on-chip RAM block L0 */
//RAML1 : origin = 0x008800, length = 0x000400 /* on-chip RAM block L1 */
RAML3 : origin = 0x009000, length = 0x001000 /* on-chip RAM block L3, for CLA run code */
OTP : origin = 0x3D7800, length = 0x000400 /* on-chip OTP */
FLASHH : origin = 0x3E8004, length = 0x009FFC /* on-chip FLASH 0x3E8002 as begin 0x3E8000 as Flashed_flag*/
//FLASHH : origin = 0x3E8000, length = 0x002000 /* on-chip FLASH */
//FLASHG : origin = 0x3EA000, length = 0x002000 /* on-chip FLASH */
//FLASHF : origin = 0x3EC000, length = 0x002000 /* on-chip FLASH */
//FLASHE : origin = 0x3EE000, length = 0x002000 /* on-chip FLASH */
//FLASHD : origin = 0x3F0000, length = 0x002000 /* on-chip FLASH */
FLASHC : origin = 0x3F2000, length = 0x002000 /* on-chip FLASH */
FLASHA : origin = 0x3F6000, length = 0x001F80 /* on-chip FLASH */
CSM_RSVD : origin = 0x3F7F80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
//BEGIN : origin = 0x3F7FF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */
BEGIN : origin = 0x3E8002, length = 0x000002 /* Part of FLASHH. . */
CSM_PWL_P0 : origin = 0x3F7FF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
IQTABLES : origin = 0x3FE000, length = 0x000B50 /* IQ Math Tables in Boot ROM */
IQTABLES2 : origin = 0x3FEB50, length = 0x00008C /* IQ Math Tables in Boot ROM */
IQTABLES3 : origin = 0x3FEBDC, length = 0x0000AA /* IQ Math Tables in Boot ROM */
ROM : origin = 0x3FF27C, length = 0x000D44 /* Boot ROM */
RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */
VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */
PAGE 1 : /* Data Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
/* Registers remain on PAGE1 */
BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */
RAMM0 : origin = 0x000080, length = 0x0007B0 /* on-chip RAM block M0, and M1 is incorporated to M0 */
// RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
DataRAM : origin = 0x008500, length = 0x0006FF /*on-chip RAM block L0,L1 */
BootFlagRAM : origin = 0x008BFF, length = 0x000001 /* on-chip RAM block L1 */
CLARAM1 : origin = 0x008C00, length = 0x000400 /* on-chip RAM block L2 */
//RAML3 : origin = 0x009000, length = 0x001000 /* on-chip RAM block L3 */
CLA1_MSGRAMLOW : origin = 0x001480, length = 0x000080
CLA1_MSGRAMHIGH : origin = 0x001500, length = 0x000080
FLASHB : origin = 0x3F4000, length = 0x002000 /* on-chip FLASH */
}
SECTIONS
{
/* Allocate program areas: */
.cinit : > FLASHH PAGE = 0
.pinit : > FLASHH, PAGE = 0
.text : > FLASHH PAGE = 0
codestart : > BEGIN PAGE = 0
IsrRamfuncs : LOAD = FLASHH,
RUN = RAMLISR_PRG,
LOAD_START(_IsrRamfuncsLoadStart),
LOAD_END(_IsrRamfuncsLoadEnd),
RUN_START(_IsrRamfuncsRunStart),
PAGE = 0
ramfuncs : LOAD = FLASHH,
RUN = RAMLAPP_PRG,
LOAD_START(_RamfuncsLoadStart),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
PAGE = 0
csmpasswds : > CSM_PWL_P0 PAGE = 0
csm_rsvd : > CSM_RSVD PAGE = 0
debug_ram : > DataRAM PAGE = 1
BootFlagRam : > BootFlagRAM PAGE = 1
/* Allocate uninitalized data sections: */
//.stack : > RAMM0 PAGE = 1
.stack : > DataRAM PAGE = 1
.ebss : > RAMM0 PAGE = 1
// .esysmem : > RAMM0 PAGE = 1
//.sysmem : > RAMM0 PAGE = 1
/* Initalized sections go in Flash */
/* For SDFlash to program these, they must be allocated to page 0 */
.econst : > FLASHH PAGE = 0
.switch : > FLASHH PAGE = 0
/* Allocate IQ math areas: */
IQmath : > FLASHA PAGE = 0 /* Math Code */
IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD
.bss_cla : > CLARAM1, PAGE = 1
.scratchpad : > CLARAM1, PAGE = 1
Cla1Prog : LOAD = FLASHH,
RUN = RAML3,
LOAD_START(_Cla1funcsLoadStart),
LOAD_END(_Cla1funcsLoadEnd),
RUN_START(_Cla1funcsRunStart),
LOAD_SIZE(_Cla1funcsLoadSize),
PAGE = 0
Cla1ToCpuMsgRAM : > CLA1_MSGRAMLOW, PAGE = 1
CpuToCla1MsgRAM : > CLA1_MSGRAMHIGH, PAGE = 1
// Cla1DataRam0 : > CLARAM0, PAGE = 1
Cla1DataRam1 : > CLARAM1, PAGE = 1
CLA1mathTables : LOAD = FLASHB,
RUN = CLARAM1,
LOAD_START(_Cla1mathTablesLoadStart),
LOAD_END(_Cla1mathTablesLoadEnd),
RUN_START(_Cla1mathTablesRunStart),
LOAD_SIZE(_Cla1mathTablesLoadSize),
PAGE = 1
CLAscratch :
{ *.obj(CLAscratch)
. += CLA_SCRATCHPAD_SIZE;
*.obj(CLAscratch_end) } > CLARAM1,
PAGE = 1
/*
IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
}
*/
/*
IQmathTables3 : > IQTABLES3, PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNasinTable.obj> (IQmathTablesRam)
}
*/
/* .reset is a standard section used by the compiler. It contains the */
/* the address of the start of _c_int00 for C Code. /*
/* When using the boot ROM this section and the CPU vector */
/* table is not needed. Thus the default type is set here to */
/* DSECT */
.reset : > RESET, PAGE = 0, TYPE = DSECT
vectors : > VECTORS PAGE = 0, TYPE = DSECT
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
Can you give me some suggestions?
