TMS320F28388D: TMS320F28388D: HRPWM with CLB cooperation

Lukas Brzyszkiewicz

Hello,

I'm preparing to our new project with 3-Level inverter. On linked post I see that is some problem with synchronization and reaction time with CLB+HRPWM.

I have two questions:

1) Can I configure HRPWM with CLB logic to protect non valid outputs (for 3-Level ANPC, 3-Level NPC, 3-Level T-Type topologies)

2) If yes - Can I predict worst reaction time (from AND output to TZ and outputs turn off)

Best regards, Ł.B.

over 5 years ago

0 Nima Eskandari over 5 years ago

TI__Guru 52200 points

I will review this with Subrahmanya and get back to you.

0 Subrahmanya over 5 years ago in reply to Nima Eskandari

TI__Mastermind 24095 points

Hi,

If you are using synchronous logic paths inside CLB then the high resolution component will be lost due to the synchronization to the CLB clock. For your Q1, resolution will be lost due to synchronization. For the worst case reaction time - the variation due to synchronizers could be up to 2 CLB clock cycles.

0 Lukas Brzyszkiewicz over 5 years ago in reply to Subrahmanya

Intellectual 335 points

Hi,

3) is there possibility to output HRPWM thru CLB and then - from CLB (for example by ANDing/ORing gates) output as HRPWM?

4) Can we predict worst case scenario for TZ with HRPWM and without synchronization on CLB?

If I understood properly - when I'm using HRPWM I cannot use CLB, because I lost asynchronous high resolution outputs?

0 Subrahmanya over 5 years ago in reply to Lukas Brzyszkiewicz

TI__Mastermind 24095 points

Hi,

3) Yes, the high resolution will be lost in CLB synchronization.
4) Worst case TZ delay is not dependent on HR or no HR. Tri-state timing is defined in "Table 5-58. ePWM Switching Characteristics" of the device data sheet.

C2000™︎ microcontrollers

C2000 microcontrollers forum

TMS320F28388D: TMS320F28388D: HRPWM with CLB cooperation