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CCS/TMS320F28335: 28335 Code help

Jiangheng Lu1
Prodigy 10 points

Part Number: TMS320F28335

Tool/software: Code Composer Studio

Hi,

  I have been trying to realize a cycle by cycle control based on ADC value.

  But I have some uS level delay between ADC input and PWM actions.

Please refer to the image, I am testing a simple logic where the PWM output is high when ADC is higher than certain threshold, while PWM is low when ADC is lower than the threshold.

I have one gpio set in the beginning and reset at the end of each ISR (yellow)

I have another gpio set in the beginning and reset at the function to read data from ADC register.(green)

and Blue is the PWM output while Purple is the ADC input

 

  Is there a way to make this delay to ~nS level?

  • 0
    TI__Guru* 82610 points

    Jiangheng,

    The ADC will have a fixed conversion time from the time it is triggered.  In this case, since the trigger is the PWM action; there will be a delay of 4 ADC Clock cycles after the signal has been sampled.  So once the PWM triggers goes active, whatever the ACQPS you have defined for the ADC + 4 ADC Clock cycles.

    The good news here is that timing is fixed; i.e. once the trigger is received from the PWM it will always be the above time from trigger to first sample ready.  So, if we want to reduce this time; we could use another PWM(assuming you have unused PWM modules) to create an "early" trigger that is the same time domain as your controlling PWM to get the trigger to happen a bit earlier in time to co-inside with the time you want to sample the signal.

    This assumes the signal of interest is not changed by the PWM action in your post; if that is the case then the delay above is the best case.

    If that is true I would check to make sure the ADC Clock is as fast as possible (25MHz) and that the ACQPS is at minimum(0).

    Let me know if the above gives a path to get the behavior you want in the system.

    Best,

    Matthew