TMS320F28388D: ADC Timing parameters tLAT and tINT for 12-bit Late Interrupt mode is different in Datasheet SPRSP14B

Hello,

I am reposting the same question again due to the images were not attached properly in my previous query.

As per the ADC Timing Diagram in the TRM, for 12-bit Late interrupt Mode, the timing parameters tLAT and tINT are same. i.e. when ADC conversion results latched into the ADCRESULTx register.

However, in the Data sheet, tINT is actually 2 to 5 SYSCLK cycles less than tLAT. Please see the columns tLAT and tINT(LATE) in the below table.

Is this due to the Errata: "ADC: DMA Read of Stale Result"? Please provide explanation for the difference in tLAT and tINT.

Best Regards

Amulrass V

Hello,

I am reposting the same question again due to the images were not attached properly in my previous query.

As per the ADC Timing Diagram in the TRM, for 12-bit Late interrupt Mode, the timing parameters tLAT and tINT are same. i.e. when ADC conversion results latched into the ADCRESULTx register.

However, in the Data sheet, tINT is actually 2 to 5 SYSCLK cycles less than tLAT. Please see the columns tLAT and tINT(LATE) in the below table.

Is this due to the Errata: "ADC: DMA Read of Stale Result"? Please provide explanation for the difference in tLAT and tINT.

Best Regards

Amulrass V

Hi,

Thanks for your reply. I understand that Tint occurs at the same time as Teoc. Then, reading of ADC result register by CPU at the ADC EOC Interrupt should not be a problem, since the minimum interrupt latency is 14 SYSCLK cycles for the TMS320F28388D device. So, this 14 SYSCLK cycles delay provides sufficient time for the ADC conversion results to be latched into the result register. Is my understanding correct?

Please let me know when the updated timing diagram will be available for ADC?

Best Regards

Amulrass V

Hi Amulrass,

Yes, if you are using late-interrupt mode to trigger a C28x CPU ISR or a CLA task, you shouldn't have any issues because the context-switch or task-start latency is longer than the couple cycles between Teoc and Tlat.  The only potential issue is if you use the DMA, because the DMA can read the result as soon as 3 cycles after the trigger is generated.

You can actually use early interrupt mode plus the ADCINTCYCLE configuration to move the ISR trigger to an arbitrary earlier time such that the results can be read just when the Tlat occurs (including accounting for any setup code in the ISR). 

I think the next revision of the datasheet will be published near end of November. You can subscribe to updates in the top right corner of the product page (https://www.ti.com/product/TMS320F28388D