TMS320F28069: power cycle

Simon: I am the Reliability engineer supporting this product line.

The main source for discussions on power cycling comes from our automotive devices where AEC-Q100 rev H has some introductory info on this. In its appendix it has an example of a traditional automotive mission profile for power cycling of 54,000 cycles. That assumed 10 power cycles per day in 15 years, hence the 54K value.

What this impacts is the modeling of thermal cycling where it changes from ambient temperature to an internal junction temperature during system self heating. These are regarded as 'cold starts'. What this impacts is the stress to the internal interconnects of the IC to the package (which is usually a bond wire or a flip chip bump) each time it turns on . The example in AEC-Q100  includes a delta T assumption of 76C for each cold start. ie/ 54K x 76C delta each time. (TI believes 76C is very aggressive profile especially an processor type of device. Also many automotive mission profiles has less # of cold starts per day - some say 3) 

Other customer applications have shared power cycling information with TI with the advent of ECO cycles in automotive vehicles. The ECO cycle is where engine turns off during a stop at traffic light but turns on when your press the peddle. Often, we see ECO cycles in addition to cold starts in a thermal cycling profile. One thing to note with the ECO cycle, the time off for each of these ECO cycles is relatively short which means the IC does not have much time to cool down to outside ambient. This is considered 'warm start' and the delta T for each cycle may only be a few degrees compared to the larger delta T of the cold start. We have seen some customer tell us they will do ~0.5 million ECO Cycles of small delta T and 10,000's of cold starts but larger delta T. 

While I have not seen much request for 30 million of power cycles, the impact of millions of warm starts with a small delta T to the IC interconnects may be relatively benign. The reliability model for assessing the interconnect is known as the Coffin-Manson. This will de-rate TI reliability temp cycling (In this case, -65C to 150C x 500 cycles) to your application case. (Use a factorial of 4 for bond wire intermetallic if you are doing this).

What I have mentioned above is just for the thermal cycling aspects. Another thing to consider is your power sequencing to make sure it follows TI datasheet recommendations and think about any voltage overshoots that could be occurring in your application during each power cycle. In you situation, you have to consider that it will occur 30 million times and if significant overshoot voltage for long pulse times, it could have a cumulative effect of applying a voltage stress. Section 5.1 1 Absolute Maximum Ratings scope this out where the device can tolerate higher voltages above recommended operating conditions for limited exposure but it advises that "Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability".