TMS320F28377S: EPwm3 ISR Stops When Using the Emulator

Andrew Barnett

I have set up EPwm3 (in up-down-count mode) to trigger an interrupt on CMPA match while up-counting. The interrupt executes but will stop at random times unless I manually clear EPwm3Regs.ETCLRbit.INT in a watch window, then it re-starts but eventually stops unless I re-clear it via watch window. This only seems to occur when I've got the emulator (XDS110) connected; when running without the emulator it fortunately doesn't seem to happen.

I am using the EPWMXLINK register to link EPwm3.TBPRD to EPwm1.TBPRD, along with EPwm2, 6, 8, 10 (EPwm3Regs.EPWMXLINK.bit.TBPRDLINK = 0;). If I disable the EPWMXLINK the problem goes away, so it appears to be related to EPWMXLINK.

The initialization and interrupt code for EPwm3 below.

Thanks in advance for any insight.

/***** Configure EPwm3 *******************************************************/

CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0; /* Disable PWM clocks */

CpuSysRegs.PCLKCR2.bit.EPWM3 = 1;

EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;

EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE;

EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;

EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;

EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;

EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;

EPwm3Regs.TBCTL.bit.FREE_SOFT = 0;

EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;

EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;

EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;

EPwm3Regs.CMPCTL.bit.LOADASYNC = SET_LOADABMODE;

EPwm3Regs.CMPCTL.bit.LOADBSYNC = SET_LOADABMODE;

EPwm3Regs.ETSEL.bit.INTSEL = ET_CTRU_CMPA;

EPwm3Regs.ETSEL.bit.INTEN = ENABLE_EPWM_INTERRUPT; /* EPwm1 interrupt is enabled */

EPwm3Regs.ETSEL.bit.SOCASELCMP = CMPA_CMPB_SOC;

EPwm3Regs.ETSEL.bit.SOCBSELCMP = CMPA_CMPB_SOC;

EPwm3Regs.ETSEL.bit.INTSELCMP = CMPA_CMPB_INT;

EPwm3Regs.ETSEL.bit.SOCASEL = ET_CTR_ZERO;

EPwm3Regs.ETSEL.bit.SOCAEN = DISABLE_EPWM_SOCA;

EPwm3Regs.ETSEL.bit.SOCBSEL = ET_CTR_ZERO;

EPwm3Regs.ETSEL.bit.SOCBEN = DISABLE_EPWM_SOCB;

EPwm3Regs.ETPS.bit.INTPRD = ET_1ST;

EPwm3Regs.ETPS.bit.INTPSSEL = USE_ETPS;

EPwm3Regs.ETPS.bit.SOCPSSEL = USE_ETPS_SOCPS;

EPwm3Regs.ETPS.bit.SOCAPRD = DISABLE_SOCA;

EPwm3Regs.ETPS.bit.SOCBPRD = DISABLE_SOCB;

EPwm3Regs.TBPRD = EPwm1Regs.TBPRD;

EPwm3Regs.CMPA.bit.CMPA = 90;

EPwm3Regs.TBPHS.bit.TBPHS = 0;

EPwm3Regs.TBCTR = 0;

EPwm3Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;

EPwm3Regs.EPWMXLINK.bit.TBPRDLINK = 0;

PieVectTable.EPWM3_INT = &ISR_EPwm;

EPwm3Regs.ETCLR.bit.INT = 1;

PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;

PieCtrlRegs.PIEIER3.bit.INTx3 = 1;

CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1; /* Enable PWM clocks */

/**************************************************************************/

The ISR code is below. The variable ISR_Counter stops incrementing when the code stops, indicating the problem.

interrupt void ISR_EPwm(void)

{

ISR_Counter++;

EPwm3Regs.ETCLR.bit.INT = 1; /* Clear PCMC EPwm2 interrupt flag */

PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;}

}

over 5 years ago

0 Nima Eskandari over 5 years ago

TI__Guru 52220 points

What is your EPWM emulation mode?

0 Andrew Barnett over 5 years ago in reply to Nima Eskandari

Intellectual 870 points

phase shift

0 Nima Eskandari over 5 years ago in reply to Andrew Barnett

TI__Guru 52220 points

Andrew I mean your emulation mode, as in what happens to your EPWM module when the debugger is connected and halts the CPU. Does your ePWM freeze or free run?

EPWM_setEmulationMode(ePWM[j], EPWM_EMULATION_FREE_RUN);

Your TBCTL.FREE_SOFT is set to 0 which is "Stop after the next time-base counter increment or decrement".

You may want to make sure this is the mode you want.

time-base counter during emulation events

00: Stop after the next time-base counter increment or decrement

01: Stop when counter completes a whole cycle:

- Up-count mode: stop when the time-base counter = period (TBCTR = TBPRD)

- Down-count mode: stop when the time-base counter = 0x00 (TBCTR = 0x00)

- Up-down-count mode: stop when the time-base counter = 0x00 (TBCTR = 0x00)

1x: Free run

0 Nima Eskandari over 5 years ago in reply to Nima Eskandari

TI__Guru 52220 points

Did you try changing the EMULATION mode?

Nima

0 Andrew Barnett over 5 years ago in reply to Nima Eskandari

Intellectual 870 points

The emulation mode was set to 00. As I understand this, emulation mode (FREE_SOFT) sets the PWM counter behavior during an emulation event, and with this setting the counter will stop after the next increment / decrement.

When I observed with the interrupt stopping as described above the emulator was connected and updating data in the Expression window but was not otherwise stopping the CPU. Is it possible in this mode that the emulator would issue a stop command of some type?

Regardless, I will change the emulation mode to Free Run and observe.

Thanks.

0 Nima Eskandari over 5 years ago in reply to Andrew Barnett

TI__Guru 52220 points

Abolutely when you have the debugger connected and you halt/do other debugger operations, you can disturb the applications timing depending on what all is running and what peripherals halt.

Nima

0 Nima Eskandari over 5 years ago in reply to Nima Eskandari

TI__Guru 52220 points

Andrew,

What's the status of your project?

Nima

0 Andrew Barnett over 5 years ago in reply to Nima Eskandari

Intellectual 870 points

made the change, and I haven't observed the problem so thanks I guess that solved it.

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TMS320F28377S: EPwm3 ISR Stops When Using the Emulator