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TMS320F28377S: Determining Sample and Hold for ADC

Bernardo de Riva
Prodigy 210 points
Part Number: TMS320F28377S
Other Parts Discussed in Thread: TL074

Hello,

We´re trying to determine the optimum sample and hold time for the ADC of the TMS320F28377s microcontroller.

We´re using the ADC in 12-bit single ended mode. According to the documentation the sample and hold can be determined using a RC model where the following parameters depend on the microcontroller:

-       n = 12

-       RON = 425 Ω

-       Ch = 14.5 pF

-       Cp = depends on the channel

and the following parameters depend on the application:

-       Error = ¼ LSB

-       Rs = ADC driving circuitsource impedance(in Ohms)

-       Cs = capacitance on ADC input pin (in pF)

For my application I´ve made the following calculations and considered the following values:

-       n = 12

-       RON = 425 Ω

-       Ch = 14.5 pF

-       Cp = 12.9 pF

-       Error = 0.25

-       Rs = 450 Ohm (this comes from the output impedance of the Op. Amp we´re using (TL074ID) plus a series resistor of 240R)

-       Cs = This depends on the filter we use with the 240R resistor in the input pin of the ADC.

If Cs = 0 (no filtering at all) and considering the Cp specified for ADCINA0 I get a minimum 181,61 ns Sample and Hold time

If Cs = 2.2 nF so the cutt of freq of my filter is 300 kHz I get a minimum S+H time of 4,715 us (which is too much for our application).

The thing is that we´ve been running some tests and if we don´t place any capacitor at the input pin of the ADC (in order to have the minimum S+H times possible) readings of the ADC are not good. We´ve seen over and undershoots and it takes long time for the signal to settle (way more than 180 ns). Precision of the ADC in this conditions is not good.

When installing a filter prior to the ADC input (for example a 240R / 2.2nF filter) signal and captures of the ADC seem to be much more precise and stable, even with 75 ns sample and hold times. Also precision of the ADC is good and we dont see any over or undershoots in the input.

Am I doing the calculations ok or am I missing someting?

How can we avoid this under and overshooting in the ADC input without increasing the S+H time?

Why do I have better results with a 300 kHZ filter even with 75 ns S+H times?

Thanks in advance.

  • 0
    TI__Guru 62975 points

    Bernardo,

    Some amount of Cs capacitance is always recommended in order to help stabilize the sampling process.  The voltage on the pin will droop when the Ch capacitor is switched on, which can cause the op-amp output to ring as it tries to match its drive level to the feedback signal until the voltage stabilizes.  Cs capacitance will help to dampen such instability.

    Another consideration is the bandwidth of the driving op-amp.  Ideally, the op-amp bandwidth should be high enough to stabilize the output level within the ACQPS window.  I see that the TL074 only has a 3-MHz GBW so I would not expect the 182-ns ACQPS window to provide optimum results without Cs.

    With the 2.2nF Cs in place and using a short ACPQS, the Ch is acquiring most of its charge from the Cs capacitor.  There is some guidance for this "Low Bandwidth" configuration in the F2806x TRM.  The values are different, but the equations and methodology would apply here.

    -Tommy

  • 0 in reply to tlee
    Prodigy 210 points

    Hi Tommy,

    Thanks for the answer, now everything makes sense. I didn´t take into account the low bandwidth of the TL074 in this case.

    In any case, following the instructions and equations of the document you recommended I should place a 237 nF in order to have a 0.25LSB error. Since I have a 240R resistor in order to limit the input current to the ADCs to 20 mA in case any input rises up to 5V, I would get a 2800 Hz cutoff freq (which is too low). Furhtermore, this cap, at 32 kHz ADC freq, leads to a 0.3 ntau which can add up to 0.88 LSB error according to the document.

    With this values I get a t S+H of 60 ns, which is very low (lower than the admissible 75ns of the TMS320F28377S).

    I was wondering how to balance S+H time, cutt of freq of the filter and admissible error.

    For example, If I place a 15 nF cap I would have:

    - 44 kHz cutoff freq (which is admisiible for my application)

    - ntau = 4.63 which reduces the error to nearly neglectable

    - t S+H = 42.77 ns which I guess I can increase so that the error is reduced

    What I try to explain is that, once I reach the maximum capacitor that I can place due to the cutoff freq, the only way of trying to minimize the error is lengthening the sample and hold time so the signal settles. Am I correct? For example, if I set a 120 ns S+H instead of 75ns I suppose precision will be better.

    Antoher thing that I suppose it would limit the error is that we´re not sampling square wave signals or signals that vary from 0 to 3V very fast, which I suppose it will also decrease the error since Cs will not dishcarge completely in any case.

    Thans again for your help.

  • 0 in reply to Bernardo de Riva
    TI__Guru 62975 points

    Bernardo de Riva said:
    I was wondering how to balance S+H time, cutt of freq of the filter and admissible error.

    I agree with your assessment that there are a lot of engineering trade-offs to consider for the system.  The optimal balance point will be determined case-by-case, depending on the requirements of the system.  In many cases, the accuracy requirements are looser than the cost requirements so developers are able to sacrifice a few LSBs of accuracy while still preserving baseline capabilities.

    Bernardo de Riva said:
    What I try to explain is that, once I reach the maximum capacitor that I can place due to the cutoff freq, the only way of trying to minimize the error is lengthening the sample and hold time so the signal settles. Am I correct? For example, if I set a 120 ns S+H instead of 75ns I suppose precision will be better.

    Yes, the ACQPS duration would be the primary method of tuning error once the RC components have been selected.

    Bernardo de Riva said:
    Antoher thing that I suppose it would limit the error is that we´re not sampling square wave signals or signals that vary from 0 to 3V very fast, which I suppose it will also decrease the error since Cs will not dishcarge completely in any case.

    Correct, the guidelines in the TRM documents tend to be conservative because they assume worst-case voltage swing scenarios.  Lesser voltage differences between the starting value of Ch vs the input pin would reduce the estimated error significantly.