The Technical Reference Manual documents the reset value for the PRD register for each CPU-Timer as 0001FFFFh. However, we consistently observe a value of 0000FFFFh (different MSW value) via the CCS debugger immediately following the debugger reset.
The documented reset value of the PRD registers also seems inconsistent considering the documented (and observed) reset value of the TIM registers. The TIM registers reset to 0000FFFFh. When a CPU-Timer is reloaded or decrements to 0, the value of the TIM register is reloaded with the value in its PRD register. The fact that these registers are documented to reset to different values doesn't appear consistent from this viewpoint.
Please provide any additional information and/or clarification possible on the reset value of the PRD registers of the CPU-Timers.
