TMS320F28069: Ramp generator for comparator not doing anything

Hello. I am trying to implement a slope compensation by using the ramp generator for the comparator. I have set Comp1Regs.RAMPMAXREF_SHDW = 0xFFFF and Comp1Regs.RAMPDECVAL_SHDW = 100. When running the program in debug, I watch the register RAMPSTS and see that it is unchanged from 0. This is strange because I set the "rampmaxref" to max. This is then probably caused by an absence of a PWMSYNC 
signal? I set DACCTL.bit.RAMPSOURCE = 0 which should make my EPWM1 as the ramp source. And I set EPwm1Regs.HRPCTL.bit.PWMSYNCSEL = 1, so the PWMSYNC should be generated when is CTR = 0. What else am I missing?

Here is the initialization code for the ramp and PWM1:

InitEPwm();							

	EALLOW;
	EPwm1Regs.TBPRD = 900;    // (100 KHz @ 60MHz clock)
	EPwm1Regs.TBCTL.bit.PRDLD = 1;          // immediate load
	EPwm1Regs.TBPHS.half.TBPHS = 0; // Set Phase register to zero
	EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Asymmetrical mode
	EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Phase loading disabled
	EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
	EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
        EPwm1Regs.TBPHS.all = 0;                // time-base Phase Register
        EPwm1Regs.TBCTR = 0;                    // time-base Counter Register
        EPwm1Regs.TBCTL.bit.FREE_SOFT = 2;      // free run on emulation suspend
	EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
	EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET; // Set PWM1A on Zero
	// Define an event (DCAEVT2) based on
	// Comparator 1 Output
	EPwm1Regs.DCTRIPSEL.bit.DCAHCOMPSEL = DC_COMP1OUT; // DCAH = Comparator 1 output
	EPwm1Regs.TZDCSEL.bit.DCAEVT2 = TZ_DCAH_HI; // DCAEVT2 = DCAH high(will become active
	// as Comparator output goes high)
	EPwm1Regs.DCACTL.bit.EVT2SRCSEL = DC_EVT2; // DCAEVT2 = DCAEVT2 (not filtered)
	EPwm1Regs.DCACTL.bit.EVT2FRCSYNCSEL = DC_EVT_ASYNC; // Take async path // Enable DCAEVT2 as a
	
	EPwm1Regs.TZSEL.bit.DCAEVT2 = 1; 
	EPwm1Regs.TZCTL.bit.TZA = TZ_FORCE_LO; // EPWM1A will go low
	EPwm1Regs.HRPCTL.bit.PWMSYNCSEL = 1; //The PWMSYNC is CTR = 0;

        EPwm1Regs.ETSEL.bit.SOCAEN = 1;         // enable SOC on A group
        EPwm1Regs.ETSEL.bit.SOCASEL = 1;        // select SOC from zero match
        EPwm1Regs.ETPS.bit.SOCAPRD = 1;         // generate pulse on 1st event
        EPwm1Regs.CMPCTL.bit.SHDWAMODE = 0;     // enable shadow mode
        EPwm1Regs.CMPCTL.bit.LOADAMODE = 2;     // reload on CTR=zero

	EDIS;

	SysCtrlRegs.PCLKCR3.bit.COMP1ENCLK = 1;               // Enable clock to the Comparator 1 block
	Comp1Regs.COMPCTL.bit.COMPDACEN = 1; //The comparator is powered up
	Comp1Regs.COMPCTL.bit.SYNCSEL = 0x1; //Synchronous version
	Comp1Regs.COMPCTL.bit.QUALSEL = 0x2; //3 clocks
	Comp1Regs.COMPCTL.bit.CMPINV = 0x0; //pass through
	Comp1Regs.COMPCTL.bit.COMPSOURCE = 0x0; //The inverting input is internal DAC
	Comp1Regs.DACCTL.bit.DACSOURCE = 1; //Internal ramp
	Comp1Regs.DACCTL.bit.RAMPSOURCE = 0; //EPWM1 is the ramp source
	Comp1Regs.RAMPDECVAL_SHDW = 100; //Initial slope
        Comp1Regs.RAMPMAXREF_SHDW = 0xFFFF;