TMS320F28388D: Ask PieVectTable

Janet Shen

Expert 7795 points

Part Number: TMS320F28388D
Other Parts Discussed in Thread: C2000WARE, TMS320F28386D

Dear Champs,

Some problems need your help and double confirmation.

1. See PIE_VECT_TABLE on f2838x_headers_nonBIOS_cpu1.cmd

PIE_VECT_TABLE : origin = 0x000D00, length = 0x000200 /* PIE Vector Table */

But we can't find full PieVectTable in 0xD00 after running InitPieVectTable. Anything is wrong?

2. I saw INT 9.9~9.12 is reserved on TRM but these were defined in f2838x_pievect.c, which is correct?

3. Could user use User Defined Trap to define their interrupt? If yes, any limitation?

If you have any suggestions, please feel free to let me know.

Thanks a lot.

over 5 years ago

0 Veena Kamath over 5 years ago

TI__Mastermind 32655 points

Hi Janet Shen,

1. Are you using C2000ware v3.03? I believe there is a bug which got introduced in 3.03. Can you try using the f2838x_headers_BIOS_cpu1.cmd file? Looks like these files got swapped as part of this release. I will raise a ticket to get this fixed in next release.

2. These interrupts should be reserved since MCAN is not available on the C28x core, it is only available on the CM subsystem.

3. I will let the interrupt expert comment on this

0 Vivek Singh over 5 years ago in reply to Veena Kamath

TI__Guru** 116081 points

Hi Janet,

3. Could user use User Defined Trap to define their interrupt? If yes, any limitation?

Yes, user can use this and there are no additional restriction on these.

Regards,

Vivek Singh

0 Janet Shen over 5 years ago in reply to Veena Kamath

TI__Expert 7795 points

Dear Venna & Vivek,

Thanks for your reply.

1. Yes, customer used the latest C2000WARE (v3.03), I will suggest them to use f2838x_headers_BIOS_cpu1.cmd and also test the older version. And wait for the next C2000WARE version to fixing this.

2. So that, there are some reserved interrupt vector in Table 3-2 is provided for CM. I studied this in TRM and found Table 41-5. NVIC Interrupt Mapping.

Does it mean Table 41-5 (TRM) map to Table3-2(DS) to achieve the interrupt of CM? How does user arrange the priority of PIE and NVIC?

3. How does user use "User Defined Trap"? Using f2838x_swprioritizedpievect.c? Or is there any symbol or structure user need to change?

If you have any suggestions, please feel free to let me know.

Thanks a lot.

0 Veena Kamath over 5 years ago in reply to Janet Shen

TI__Mastermind 32655 points

Hi Janet Shen,

Janet Shen said:
2. So that, there are some reserved interrupt vector in Table 3-2 is provided for CM. I studied this in TRM and found Table 41-5. NVIC Interrupt Mapping.

The MCAN interrupts are only available on the CM core and not in C28x core. So the interrupts will be present on NVIC, and not in PIE.

Regards,

Veena

0 Frederick LIN over 5 years ago in reply to Veena Kamath

Intellectual 600 points

Hi Veena,

I have tried some version combinations, but the same problem still exists in all below combinations.

Chip: TMS320F28386D

CCS: 9.3.0.00012

use f2838x_headers_BIOS_cpu1.cmd below:

compiler 18.12.4, C2000Ware 3.2

compiler 20.2.2, C2000Ware 3.2

compiler 18.12.4, C2000Ware 3.3

compiler 20.2.2, C2000Ware 3.3

compiler 20.2.1, C2000Ware 3.3

compiler 18.12.1, C2000Ware 2.1

use f2838x_headers_nonBIOS_cpu1.cmd below:

compiler 18.12.1, C2000Ware 2.1

my test code is very simple:

int main(void)
{
// This function is found in the F2838x_PieCtrl.c file.
InitPieCtrl();

// Disable CPU interrupts and clear all CPU interrupt flags:
IER = 0x0000;
IFR = 0x0000;

InitPieVectTable();

return 0;
}

Could you give us other suggestions?

Thanks.

0 Veena Kamath over 5 years ago in reply to Frederick LIN

TI__Mastermind 32655 points

Hi Frederick,

I am unable to reproduce the issue. In fact, the usage of nonBIOS and BIOS linker command file should not matter. I used C2000ware 3.3, nonBIOS.cmd file, compiler v18.12.1 and I could see PIecVectTable getting initialized.

Note that the InitPieVectTable function does not initialize the first 3 vectors, since this is initialized by the Boot code. Even in the image Janet shared in the initial query, I see that the PIevcet table is initialized to some value. Are you expecting some different value?

To make sure InitPieVectTable actually writes to the 0xD00 location, you can try clearing some of those memory locations (address > 0xD06) and rerun the InitPieVectTable function and see if the value is written correctly.

Regards,

Veena

0 Vasudha Bhadoria over 5 years ago in reply to Janet Shen

TI__Genius 10845 points

Hi Janet,

3. How does user use "User Defined Trap"? Using f2838x_swprioritizedpievect.c? Or is there any symbol or structure user need to change?

If you have any suggestions, please feel free to let me know.

USER1 – USER12 are user-defined software interrupts which are non-maskable interrupts. These can be raised through TRAP instruction only.

// Code for raising user interrupts:

__asm(" TRAP #20");   // This will raise USER1 interrupt. 20 is the vector id



// USER1 ISR

__interrupt void user1ISR(void)

{

   temp1++;

   temp2++;

}

Thanks

Vasudha

0 Frederick LIN over 5 years ago in reply to Veena Kamath

Intellectual 600 points

Hi Veena,

1. Is the problem may be happend dependent on CCS version or XDS110 Debug probe? What is your ccs vesion that unable to reproduce the issue?

2. I try again and there are difference value after InitPieVectTable() function. Sorry I am not true what you mean to " some value".

3. The value can be write correctly after InitPieVectTable(). I write 0xD06 as 0xFFFF, and this value be writen to 0x270B after InitPieVectTable().

0 Veena Kamath over 5 years ago in reply to Frederick LIN

TI__Mastermind 32655 points

Hi Frederick,

Frederick LIN said:
1. Is the problem may be happend dependent on CCS version or XDS110 Debug probe? What is your ccs vesion that unable to reproduce the issue?

I am using CCS v10.0.0. I am using F28388D controlcard and is using th XDS100v2 emulator which comes with it.

Frederick LIN said:
2. I try again and there are difference value after InitPieVectTable() function. Sorry I am not true what you mean to " some value".

What I meant was, in the image posted in the initial query, I see that the locations 0xD06 and higher is initialized with some value, I presume this is initialized by the InitPieVectTable. Probably, I did not get your question correct. Are you saying the initialized values are incorrect? Or are you seeing these memory locations as 0.

Regards,

Veena

0 Frederick LIN over 5 years ago in reply to Veena Kamath

Intellectual 600 points

Hi Veena,

I think that the PieVectTable values are no problem between address 0xD00~0xDFF. Our main problem is address 0xE00~0xEFF always show message "Memory map prevented reading 0x00000Exx". It is happened no matter the entry point, InitPieCtrl() or InitPieVectTable() finished.

Regards,

Frederick

0 Veena Kamath over 5 years ago in reply to Frederick LIN

TI__Mastermind 32655 points

Oh ok. Now I understood your question. This is a CCS related issue. I will raise a ticket to get this fixed.

As a workaround, you can update the gel file (available in <CCS path>\ccs_base\emulation\gel\<device>.gel as below:

GEL_MapAddStr(0x00000D00,0, 0x100, "R|W|AS2",0); /* PIE Vector Table

GEL_MapAddStr(0x00000D00,0, 0x200, "R|W|AS2",0); /* PIE Vector Table

and

GEL_MapAddStr(0x00000D00,1, 0x100, "R|W|AS2",0); /* PIE Vector Table

GEL_MapAddStr(0x00000D00,1, 0x200, "R|W|AS2",0); /* PIE Vector Table

Let me know if this works.

Regards,

Veena

0 Frederick LIN over 5 years ago in reply to Veena Kamath

Intellectual 600 points

Hi Veena,

It works!!, All address have init value between address 0xD00 to 0xEFF. Thanks a lot.

0 Janet Shen over 5 years ago in reply to Veena Kamath

TI__Expert 7795 points

Dear Veena,

If user only used PIE on CPU1/CPU2 and do not use CM at this moment, could they use INT 9.9~9.12 to define as user defined interrupt?

Because Frederick need to generate more user defined interrupt, they hope to know which interrupts they could use to re-define.

If you have any suggestions, please feel free to let us know.

Thanks a lot.

0 Vivek Singh over 5 years ago in reply to Janet Shen

TI__Guru** 116081 points

Hi Janet,

Yes, user can use them as SW interrupt but please see below note (from TRM) on updating the PIE IFR flag by software.

Regards,

Vivek Singh

0 Janet Shen over 5 years ago in reply to Vivek Singh

TI__Expert 7795 points

Dear Vivek,

Please kindly let me double confirm this usage.

So that, if we only use C28x and do not use CM, we could reuse some unused PIE vector from CM, right?

Even we could use the unused PIE vector, no matter C28(CPU1/CPU2) or CM, right?

If you have any suggestions, please feel free to let me know.

Thanks a lot.

0 Janet Shen over 5 years ago in reply to Janet Shen

TI__Expert 7795 points

Dear Vivek,

Sorry, could you kindly help me confirm this concern?

"If user only use C28x and do not use CM, we could reuse each unused PIE vector from CM, right? Even we could use the unused PIE vector, no matter C28(CPU1/CPU2) or CM, right? "

Thanks a lot.

0 Vivek Singh over 5 years ago in reply to Janet Shen

TI__Guru** 116081 points

Yes, you can use any unused PIE vector.

Regards,

Vivek Singh

0 Janet Shen over 5 years ago in reply to Vivek Singh

TI__Expert 7795 points

Dear Veena & Vivek,

Thanks for your help.

We got the clear answers from above problems.

Many thanks.

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TMS320F28388D: Ask PieVectTable