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Hi,
my customer build a project and no error report.
But when they load it on the board, the error is as below:
We are not sure if the problem is caused by the fact that we merge different flash sectors together as below in cmd file. But I believe it's okay to merge different sectors(from sector 0 to sector 15) into single space, right?
Then what may be the problem?
Howard,
Can you ask customer to do an erase first using the on-chip CCS Flash Plugin? Please let me know whether it succeeds or not.
Did they get this error when they did CCS debug window -> Run -> Load -> Load program?
Thanks and regards,
Vamsi
Vamsi,
Erase will succeed and no error is reported.
The error we got is when we load image with Uniflash.
We also tried with CCS8.3 with Run -> Load -> Load program, the error is similar:
Howard,
Ok, thank you for the details. There is no issue in merging flash sectors in the linker cmd file.
Are they able to successfully erase/program this board previously? Did any recent change in the project caused this issue?
Can you send the linker cmd file?
In the erase settings in the plugin GUI, make sure the entire flash erase is chosen for program load.
Thanks and regards,
Vamsi
Vamsi,
they haven't successfully program the board with their code before. But they've programmed with TI's example code successfully before.
They have chosen flashbank0 and bank1 sector 0-15 to erase and it report no error.
Their code is based on their original F28032's code.
The cmd file is attached:
MEMORY
{
PAGE 0: /* Program Memory */
PAGE 1: /* Data Memory */
ADCA_RESULT : origin = 0x000B00, length = 0x000020
ADCB_RESULT : origin = 0x000B20, length = 0x000020
ADCC_RESULT : origin = 0x000B40, length = 0x000020
ADCA : origin = 0x007400, length = 0x000080
ADCB : origin = 0x007480, length = 0x000080
ADCC : origin = 0x007500, length = 0x000080
ANALOG_SUBSYS : origin = 0x05D700, length = 0x000100
CANA : origin = 0x048000, length = 0x000800
CANB : origin = 0x04A000, length = 0x000800
CLA1 : origin = 0x001400, length = 0x000080 /* CLA registers */
CLAPROMCRC : origin = 0x0061C0, length = 0x000020
CLB_XBAR : origin = 0x007A40, length = 0x000040
CMPSS1 : origin = 0x005C80, length = 0x000020
CMPSS2 : origin = 0x005CA0, length = 0x000020
CMPSS3 : origin = 0x005CC0, length = 0x000020
CMPSS4 : origin = 0x005CE0, length = 0x000020
CMPSS5 : origin = 0x005D00, length = 0x000020
CMPSS6 : origin = 0x005D20, length = 0x000020
CMPSS7 : origin = 0x005D40, length = 0x000020
CPU_TIMER0 : origin = 0x000C00, length = 0x000008 /* CPU Timer0 registers */
CPU_TIMER1 : origin = 0x000C08, length = 0x000008 /* CPU Timer1 registers */
CPU_TIMER2 : origin = 0x000C10, length = 0x000008 /* CPU Timer2 registers */
DACA : origin = 0x005C00, length = 0x000010
DACB : origin = 0x005C10, length = 0x000010
DCC0 : origin = 0x05E700, length = 0x000040
DCSM_BANK0_Z1 : origin = 0x05F000, length = 0x000030
DCSM_BANK0_Z2 : origin = 0x05F040, length = 0x000030
DCSM_BANK1_Z1 : origin = 0x05F100, length = 0x000030
DCSM_BANK1_Z2 : origin = 0x05F140, length = 0x000030
DCSM_COMMON : origin = 0x05F070, length = 0x000010 /* Common Dual code security module registers */
DMA : origin = 0x001000, length = 0x000200
ECAP1 : origin = 0x005200, length = 0x000040 /* Enhanced Capture 1 registers */
ECAP2 : origin = 0x005240, length = 0x000040 /* Enhanced Capture 2 registers */
ECAP3 : origin = 0x005280, length = 0x000040 /* Enhanced Capture 3 registers */
ECAP4 : origin = 0x0052C0, length = 0x000040 /* Enhanced Capture 4 registers */
ECAP5 : origin = 0x005300, length = 0x000040 /* Enhanced Capture 5 registers */
ECAP6 : origin = 0x005340, length = 0x000040 /* Enhanced Capture 6 registers */
ECAP7 : origin = 0x005380, length = 0x000040 /* Enhanced Capture 7 registers */
PGA1 : origin = 0x005B00, length = 0x000010
PGA2 : origin = 0x005B10, length = 0x000010
PGA3 : origin = 0x005B20, length = 0x000010
PGA4 : origin = 0x005B30, length = 0x000010
PGA5 : origin = 0x005B40, length = 0x000010
PGA6 : origin = 0x005B50, length = 0x000010
PGA7 : origin = 0x005B60, length = 0x000010
EPWM1 : origin = 0x004000, length = 0x000100 /* Enhanced PWM 1 registers */
EPWM2 : origin = 0x004100, length = 0x000100 /* Enhanced PWM 2 registers */
EPWM3 : origin = 0x004200, length = 0x000100 /* Enhanced PWM 3 registers */
EPWM4 : origin = 0x004300, length = 0x000100 /* Enhanced PWM 4 registers */
EPWM5 : origin = 0x004400, length = 0x000100 /* Enhanced PWM 5 registers */
EPWM6 : origin = 0x004500, length = 0x000100 /* Enhanced PWM 6 registers */
EPWM7 : origin = 0x004600, length = 0x000100 /* Enhanced PWM 7 registers */
EPWM8 : origin = 0x004700, length = 0x000100 /* Enhanced PWM 8 registers */
EPWM_XBAR : origin = 0x007A00, length = 0x000040
EQEP1 : origin = 0x005100, length = 0x000040 /* Enhanced QEP 1 registers */
EQEP2 : origin = 0x005140, length = 0x000040 /* Enhanced QEP 2 registers */
FLASH0_CTRL : origin = 0x05F800, length = 0x000300
FLASH0_ECC : origin = 0x05FB00, length = 0x000040
FSITXA : origin = 0x006600, length = 0x000080
FSIRXA : origin = 0x006680, length = 0x000080
GPIOCTRL : origin = 0x007C00, length = 0x000200 /* GPIO control registers */
GPIODAT : origin = 0x007F00, length = 0x000040 /* GPIO data registers */
I2CA : origin = 0x007300, length = 0x000040 /* I2C-A registers */
INPUT_XBAR : origin = 0x007900, length = 0x000020
LINA : origin = 0x006A00, length = 0x000100
LINB : origin = 0x006B00, length = 0x000100
MEMCFG : origin = 0x05F400, length = 0x000080 /* Mem Config registers */
ACCESSPROTECTION : origin = 0x05F4C0, length = 0x000040 /* Access Protection registers */
MEMORYERROR : origin = 0x05F500, length = 0x000040 /* Access Protection registers */
NMIINTRUPT : origin = 0x007060, length = 0x000010 /* NMI Watchdog Interrupt Registers */
OUTPUT_XBAR : origin = 0x007A80, length = 0x000040
PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */
PIE_VECT : origin = 0x000D00, length = 0x000200 /* PIE Vector Table */
PMBUSA : origin = 0x006400, length = 0x000020
SCIA : origin = 0x007200, length = 0x000010 /* SCI-A registers */
SCIB : origin = 0x007210, length = 0x000010 /* SCI-B registers */
SDFM1 : origin = 0x005E00, length = 0x000080 /* Sigma delta 1 registers */
SPIA : origin = 0x006100, length = 0x000010
SPIB : origin = 0x006110, length = 0x000010
WD : origin = 0x007000, length = 0x000040
DMACLASRCSEL : origin = 0x007980, length = 0x000040
DEV_CFG : origin = 0x05D000, length = 0x000180
CLK_CFG : origin = 0x05D200, length = 0x000100
CPU_SYS : origin = 0x05D300, length = 0x000100
PERIPH_AC : origin = 0x05D500, length = 0x000200
ERAD_GLOBAL : origin = 0x05E800, length = 0x000013
ERAD_HWBP1 : origin = 0x05E900, length = 0x000008
ERAD_HWBP2 : origin = 0x05E908, length = 0x000008
ERAD_HWBP3 : origin = 0x05E910, length = 0x000008
ERAD_HWBP4 : origin = 0x05E918, length = 0x000008
ERAD_HWBP5 : origin = 0x05E920, length = 0x000008
ERAD_HWBP6 : origin = 0x05E928, length = 0x000008
ERAD_HWBP7 : origin = 0x05E930, length = 0x000008
ERAD_HWBP8 : origin = 0x05E938, length = 0x000008
ERAD_CTR1 : origin = 0x05E980, length = 0x000010
ERAD_CTR2 : origin = 0x05E990, length = 0x000010
ERAD_CTR3 : origin = 0x05E9A0, length = 0x000010
ERAD_CTR4 : origin = 0x05E9B0, length = 0x000010
XBAR : origin = 0x007920, length = 0x000020
SYNC_SOC : origin = 0x007940, length = 0x000010
XINT : origin = 0x007070, length = 0x000010
IsrVariable : origin = 0x000700, length = 0x0000E0 /* ISR variable define */
}
SECTIONS
{
/*** PIE Vect Table and Boot ROM Variables Structures ***/
UNION run = PIE_VECT, PAGE = 1
{
PieVectTableFile
GROUP
{
EmuKeyVar
EmuBModeVar
FlashCallbackVar
FlashScalingVar
}
}
AdcaResultFile : > ADCA_RESULT, PAGE = 1
AdcbResultFile : > ADCB_RESULT, PAGE = 1
AdccResultFile : > ADCC_RESULT, PAGE = 1
AdcaRegsFile : > ADCA, PAGE = 1
AdcbRegsFile : > ADCB, PAGE = 1
AdccRegsFile : > ADCC, PAGE = 1
AnalogSubsysRegsFile : > ANALOG_SUBSYS, PAGE = 1
CanaRegsFile : > CANA, PAGE = 1
CanbRegsFile : > CANB, PAGE = 1
Cla1RegsFile : > CLA1, PAGE = 1
Cla1SoftIntRegsFile : > PIE_CTRL, PAGE = 1, type=DSECT
ClaPromCrc0RegsFile : > CLAPROMCRC, PAGE = 1
ClbXbarRegsFile : > CLB_XBAR, PAGE = 1
Cmpss1RegsFile : > CMPSS1, PAGE = 1
Cmpss2RegsFile : > CMPSS2, PAGE = 1
Cmpss3RegsFile : > CMPSS3, PAGE = 1
Cmpss4RegsFile : > CMPSS4, PAGE = 1
Cmpss5RegsFile : > CMPSS5, PAGE = 1
Cmpss6RegsFile : > CMPSS6, PAGE = 1
Cmpss7RegsFile : > CMPSS7, PAGE = 1
CpuTimer0RegsFile : > CPU_TIMER0, PAGE = 1
CpuTimer1RegsFile : > CPU_TIMER1, PAGE = 1
CpuTimer2RegsFile : > CPU_TIMER2, PAGE = 1
DacaRegsFile : > DACA PAGE = 1
DacbRegsFile : > DACB PAGE = 1
Dcc0RegsFile : > DCC0 PAGE = 1
DcsmBank0Z1RegsFile : > DCSM_BANK0_Z1, PAGE = 1
DcsmBank0Z2RegsFile : > DCSM_BANK0_Z2, PAGE = 1
DcsmBank1Z1RegsFile : > DCSM_BANK1_Z1, PAGE = 1
DcsmBank1Z2RegsFile : > DCSM_BANK1_Z2, PAGE = 1
DcsmCommonRegsFile : > DCSM_COMMON, PAGE = 1
DmaRegsFile : > DMA, PAGE = 1
ECap1RegsFile : > ECAP1, PAGE = 1
ECap2RegsFile : > ECAP2, PAGE = 1
ECap3RegsFile : > ECAP3, PAGE = 1
ECap4RegsFile : > ECAP4, PAGE = 1
ECap5RegsFile : > ECAP5, PAGE = 1
ECap6RegsFile : > ECAP6, PAGE = 1
ECap7RegsFile : > ECAP7, PAGE = 1
Pga1RegsFile : > PGA1, PAGE = 1
Pga2RegsFile : > PGA2, PAGE = 1
Pga3RegsFile : > PGA3, PAGE = 1
Pga4RegsFile : > PGA4, PAGE = 1
Pga5RegsFile : > PGA5, PAGE = 1
Pga6RegsFile : > PGA6, PAGE = 1
Pga7RegsFile : > PGA7, PAGE = 1
EPwm1RegsFile : > EPWM1, PAGE = 1
EPwm2RegsFile : > EPWM2, PAGE = 1
EPwm3RegsFile : > EPWM3, PAGE = 1
EPwm4RegsFile : > EPWM4, PAGE = 1
EPwm5RegsFile : > EPWM5, PAGE = 1
EPwm6RegsFile : > EPWM6, PAGE = 1
EPwm7RegsFile : > EPWM7, PAGE = 1
EPwm8RegsFile : > EPWM8, PAGE = 1
EPwmXbarRegsFile : > EPWM_XBAR PAGE = 1
EQep1RegsFile : > EQEP1, PAGE = 1
EQep2RegsFile : > EQEP2, PAGE = 1
EradGlobalRegsFile : > ERAD_GLOBAL, PAGE = 1
EradHWBP1RegsFile : > ERAD_HWBP1, PAGE = 1
EradHWBP2RegsFile : > ERAD_HWBP2, PAGE = 1
EradHWBP3RegsFile : > ERAD_HWBP3, PAGE = 1
EradHWBP4RegsFile : > ERAD_HWBP4, PAGE = 1
EradHWBP5RegsFile : > ERAD_HWBP5, PAGE = 1
EradHWBP6RegsFile : > ERAD_HWBP6, PAGE = 1
EradHWBP7RegsFile : > ERAD_HWBP7, PAGE = 1
EradHWBP8RegsFile : > ERAD_HWBP8, PAGE = 1
EradCounter1RegsFile : > ERAD_CTR1, PAGE = 1
EradCounter2RegsFile : > ERAD_CTR2, PAGE = 1
EradCounter3RegsFile : > ERAD_CTR3, PAGE = 1
EradCounter4RegsFile : > ERAD_CTR4, PAGE = 1
Flash0CtrlRegsFile : > FLASH0_CTRL PAGE = 1
Flash0EccRegsFile : > FLASH0_ECC PAGE = 1
FsiTxaRegsFile : > FSITXA PAGE = 1
FsiRxaRegsFile : > FSIRXA PAGE = 1
GpioCtrlRegsFile : > GPIOCTRL, PAGE = 1
GpioDataRegsFile : > GPIODAT, PAGE = 1
I2caRegsFile : > I2CA, PAGE = 1
InputXbarRegsFile : > INPUT_XBAR PAGE = 1
XbarRegsFile : > XBAR PAGE = 1
LinaRegsFile : > LINA, PAGE = 1
LinbRegsFile : > LINB, PAGE = 1
MemCfgRegsFile : > MEMCFG, PAGE = 1
AccessProtectionRegsFile : > ACCESSPROTECTION, PAGE = 1
MemoryErrorRegsFile : > MEMORYERROR, PAGE = 1
NmiIntruptRegsFile : > NMIINTRUPT, PAGE = 1
OutputXbarRegsFile : > OUTPUT_XBAR, PAGE = 1
PieCtrlRegsFile : > PIE_CTRL, PAGE = 1
PmbusaRegsFile : > PMBUSA, PAGE = 1
SciaRegsFile : > SCIA, PAGE = 1
ScibRegsFile : > SCIB, PAGE = 1
Sdfm1RegsFile : > SDFM1, PAGE = 1
SpiaRegsFile : > SPIA, PAGE = 1
SpibRegsFile : > SPIB, PAGE = 1
WdRegsFile : > WD, PAGE = 1
DmaClaSrcSelRegsFile : > DMACLASRCSEL PAGE = 1
DevCfgRegsFile : > DEV_CFG, PAGE = 1
ClkCfgRegsFile : > CLK_CFG, PAGE = 1
CpuSysRegsFile : > CPU_SYS, PAGE = 1
SysPeriphAcRegsFile : > PERIPH_AC, PAGE = 1
SyncSocRegsFile : > SYNC_SOC, PAGE = 1
XintRegsFile : > XINT, PAGE = 1
IsrVariableFile : > IsrVariable PAGE = 1
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
MEMORY
{
PAGE 0 :
/* BEGIN is used for the "boot to Flash" bootloader mode */
BEGIN : origin = 0x080000, length = 0x000002
RAMM0 : origin = 0x0000F3, length = 0x00030D
RAML0_PRG : origin = 0x008000, length = 0x000920
RAML0BOOT_PRG : origin = 0x008920, length = 0x000020
//RAMLS0 : origin = 0x008000, length = 0x000800
//RAMLS1 : origin = 0x008800, length = 0x000800
//RAMLS2 : origin = 0x009000, length = 0x000800
RAMLS3 : origin = 0x009800, length = 0x000800
RAMLS4 : origin = 0x00A000, length = 0x000800
RESET : origin = 0x3FFFC0, length = 0x000002
/* Flash sectors */
/* BANK 0 */
// FLASH_BANK0_SEC0 : origin = 0x080002, length = 0x000FFE /* on-chip Flash */
// FLASH_BANK0_SEC1 : origin = 0x081000, length = 0x001000 /* on-chip Flash */
// FLASH_BANK0_SEC2 : origin = 0x082000, length = 0x001000 /* on-chip Flash */
// FLASH_BANK0_SEC3 : origin = 0x083000, length = 0x001000 /* on-chip Flash */
// FLASH_BANK0_SEC4 : origin = 0x084000, length = 0x001000 /* on-chip Flash */
// FLASH_BANK0_SEC5 : origin = 0x085000, length = 0x001000 /* on-chip Flash */
// FLASH_BANK0_SEC6 : origin = 0x086000, length = 0x001000 /* on-chip Flash */
// FLASH_BANK0_SEC7 : origin = 0x087000, length = 0x001000 /* on-chip Flash */
// FLASH_BANK0_SEC8 : origin = 0x088000, length = 0x001000 /* on-chip Flash */
// FLASH_BANK0_SEC9 : origin = 0x089000, length = 0x001000 /* on-chip Flash */
// FLASH_BANK0_SEC10 : origin = 0x08A000, length = 0x001000 /* on-chip Flash */
// FLASH_BANK0_SEC11 : origin = 0x08B000, length = 0x001000 /* on-chip Flash */
// FLASH_BANK0_SEC12 : origin = 0x08C000, length = 0x001000 /* on-chip Flash */
// FLASH_BANK0_SEC13 : origin = 0x08D000, length = 0x001000 /* on-chip Flash */
// FLASH_BANK0_SEC14 : origin = 0x08E000, length = 0x001000 /* on-chip Flash */
// FLASH_BANK0_SEC15 : origin = 0x08F000, length = 0x001000 /* on-chip Flash */
APPVEC : origin = 0x080002, length = 0x000010
FLASH : origin = 0x080012, length = 0x00DFED
APPCRC : origin = 0x08DFFF, length = 0x000001
BOOTVEC : origin = 0x08E000, length = 0x000040
RAMFLASH : origin = 0x08E040, length = 0x000020
LIB_FLASH : origin = 0x08E060, length = 0x0001D8
FLASH_BOOT : origin = 0x08E238, length = 0x000D48 /* on-chip FLASH */
// FLASH_BANK0_SEC0 : origin = 0x080002, length = 0x000300 /* on-chip Flash */
// FLASH_BANK0_SEC0 : origin = 0x080002, length = 0x000FFE /* on-chip Flash */
// FLASH_BANK0_SEC1 : origin = 0x081000, length = 0x001000 /* on-chip Flash */
// FLASH_BANK0_SEC2 : origin = 0x082000, length = 0x001000 /* on-chip Flash */
// FLASH_BANK0_SEC3 : origin = 0x083000, length = 0x001000 /* on-chip Flash */
// FLASH_BANK0_SEC4 : origin = 0x084000, length = 0x001000 /* on-chip Flash */
// FLASH_BANK0_SEC5 : origin = 0x085000, length = 0x001000 /* on-chip Flash */
// FLASH_BANK0_SEC6 : origin = 0x086000, length = 0x001000 /* on-chip Flash */
// FLASH_BANK0_SEC7 : origin = 0x087000, length = 0x001000 /* on-chip Flash */
// FLASH_BANK0_SEC8 : origin = 0x088000, length = 0x001000 /* on-chip Flash */
// FLASH_BANK0_SEC9 : origin = 0x089000, length = 0x001000 /* on-chip Flash */
// FLASH_BANK0_SEC10 : origin = 0x08A000, length = 0x001000 /* on-chip Flash */
// FLASH_BANK0_SEC11 : origin = 0x08B000, length = 0x001000 /* on-chip Flash */
// FLASH_BANK0_SEC12 : origin = 0x08C000, length = 0x001000 /* on-chip Flash */
// FLASH_BANK0_SEC13 : origin = 0x08D000, length = 0x001000 /* on-chip Flash */
// FLASH_BANK0_SEC14 : origin = 0x08E000, length = 0x001000 /* on-chip Flash */
// FLASH_BANK0_SEC15 : origin = 0x08F000, length = 0x001000 /* on-chip Flash */
IQTABLES : origin = 0x3FF000, length = 0x000b50
ROM : origin = 0x3FFB50, length = 0x000386
RSVD1 : origin = 0x3FFED6, length = 0x0000E3
FLASH_API : origin = 0x3FFFB9, length = 0x000001
VERSION : origin = 0x3FFFBA, length = 0x000002
CHECKSUM : origin = 0x3FFFBC, length = 0x000004
VECTORS : origin = 0x3FFFC2, length = 0x000040
FLASH_BANK1_SEC0 : origin = 0x090000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC1 : origin = 0x091000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC2 : origin = 0x092000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC3 : origin = 0x093000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC4 : origin = 0x094000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC5 : origin = 0x095000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC6 : origin = 0x096000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC7 : origin = 0x097000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC8 : origin = 0x098000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC9 : origin = 0x099000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC10 : origin = 0x09A000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC11 : origin = 0x09B000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC12 : origin = 0x09C000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC13 : origin = 0x09D000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC14 : origin = 0x09E000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC15 : origin = 0x09F000, length = 0x000FF0 /* on-chip Flash */
// FLASH_BANK1_SEC15_RSVD : origin = 0x09FFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
PAGE 1 :
BOOT_RSVD : origin = 0x000002, length = 0x0000F1 /* Part of M0, BOOT rom will use this for stack */
RAMM1 : origin = 0x000400, length = 0x000300 /* on-chip RAM block M1 */
RAML0_DATA : origin = 0x008940, length = 0x00600
// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
RAMLS5 : origin = 0x00A800, length = 0x000800
RAMLS6 : origin = 0x00B000, length = 0x000800
RAMLS7 : origin = 0x00B800, length = 0x000800
RAMGS0 : origin = 0x00C000, length = 0x002000
RAMGS1 : origin = 0x00E000, length = 0x002000
RAMGS2 : origin = 0x010000, length = 0x002000
RAMGS3 : origin = 0x012000, length = 0x001FF8
// RAMGS3_RSVD : origin = 0x013FF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
}
SECTIONS
{
codestart : > BEGIN, PAGE = 0, ALIGN(4)
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
.cinit : > FLASH PAGE = 0
.text : > FLASH PAGE = 0
.init : LOAD = FLASH_BOOT PAGE = 0
{
/*
DSP280x_Adc.obj (.text)
DSP280x_EPwm.obj (.text)
DSP280x_ECap.obj (.text)
*/
DSP280x_PieCtrl.obj (.text)
DSP280x_PieVect.obj (.text)
DSP280x_CpuTimers.obj (.text)
DSP280x_DefaultIsr.obj (.text)
// DSP280x_ECan.obj (.text)
DSP280x_Gpio.obj (.text)
DSP280x_I2C.obj (.text)
DSP280x_MemCopy.obj (.text)
DSP280x_SysCtrl.obj (.text)
}
.cal : > LIB_FLASH PAGE = 0
{
// -lrts2800_ml.lib <fd_mpy.obj u_div.obj
// l_div.obj fd_tol.obj fs_tofd.obj fs_tou.obj
// boot.obj exit.obj _lock.obj args_main.obj> (.text)
// -lrts2800_ml.lib <exit.obj _lock.obj> (.cinit)
}
bootramfuncs : LOAD = RAMFLASH,
RUN = RAML0BOOT_PRG,
LOAD_START(_BootRamfuncsLoadStart),
LOAD_END(_BootRamfuncsLoadEnd),
RUN_START(_BootRamfuncsRunStart),
PAGE = 0
IsrRamfuncs : LOAD = FLASH,
RUN = RAML0_PRG,
LOAD_START(_IsrRamfuncsLoadStart),
LOAD_END(_IsrRamfuncsLoadEnd),
RUN_START(_IsrRamfuncsRunStart),
PAGE = 0
//lzy 2010624 for cla
/* Cla1Prog : LOAD = FLASH,
RUN = RAMCLA_PRG,
LOAD_START(_Cla1funcsLoadStart),
LOAD_END(_Cla1funcsLoadEnd),
RUN_START(_Cla1funcsRunStart),
PAGE = 0
*/
/* csmpasswds : > CSM_PWL_P0 PAGE = 0*/
.appvec : > APPVEC PAGE = 0
appcrc : > APPCRC PAGE = 0
.bootvec : > BOOTVEC PAGE = 0
FlashBoot : > FLASH_BOOT PAGE = 0
// csmpasswds : > CSM_PWL PAGE = 0
// csm_rsvd : > CSM_RSVD PAGE = 0
/* Allocate uninitalized data sections: */
.stack : > RAMM1 PAGE = 1
.ebss : > RAML0_DATA PAGE = 1
/*.esysmem : > RAML3 PAGE = 1*/
// SinbackbakFile : > FLASH PAGE = 0//lzy 20100624 for cla
/* Initalized sections go in Flash */
/* For SDFlash to program these, they must be allocated to page 0 */
.econst : > FLASH PAGE = 0
.switch : > FLASH PAGE = 0
.const : > FLASH PAGE = 0
/* Allocate IQ math areas: */
IQmath : > FLASH PAGE = 0 /* Math Code */
IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD
/* .reset is a standard section used by the compiler. It contains the */
/* the address of the start of _c_int00 for C Code. /*
/* When using the boot ROM this section and the CPU vector */
/* table is not needed. Thus the default type is set here to */
/* DSECT */
vectors : > VECTORS PAGE = 0, TYPE = DSECT
/*******************************************************************/
/* These addresses reside in the RAM section and are hard coded */
/* in the linker command files because the liker cannot be trusted */
/* to put them where we want them. They have to stay the same for */
/* the first and second level boot loaders and the application. */
/*******************************************************************/
/* ESNA protocal variants define*/
{_Hardware_Version = 0x07E0;}/* 4-byte 0x07E0 and 0x07E1 */
{_spec_number = 0x07E2;}/*from 0x07E2 to 0x07F1, 32-bytes for 16 chars*/
/*common variants*/
{_ulENP_Lo_SN = 0x07F2;}/*Hi & Lo Extended Emerson Serial Number */
{_ulENP_Lo_SN_H = 0x07F3;}/* Note7(A23-A16),Hi_SN(A15-A00),Lo_SN(A23-A00)*/
{_ulENP_Hi_SN = 0x07F4;}
{_ulENP_Hi_SN_H = 0x07F5;}/* all 48 bits */
{_g_u16WriteNumber = 0x07F6;}
{_g_u16I2CErrorType = 0x07F7;}
{_g_u16MdlStatus = 0x07F8;}
{_g_u16ActionReady = 0x07F9;}
{_u16WaitLoopCount = 0x07FA;}
{_g_u16RdEepromOk = 0x07FB;}
// {_RatedCurrent = 0x07FC;} //have be removed
{_u16AddIdentify = 0x07FD;}
{_g_u16MdlAddr = 0x07FE;}
{_u16FromApplication = 0x07FF;}
{_g_fRdTemp = 0x8F40;}
{_ECana32Temp = 0x8F42;}
{_g_lq10AcVrmsSampSysa =0x8F44;}
{_g_lq10AcVrmsSampSysb =0x8F46;}
{_g_lq10VpfcSampSys =0x8F48;}
{_g_lq10VpfcConSys =0x8F4A;}
{_g_lq12VoltSampSysa =0x8F4C;}
{_g_lq12VoltSampSysb =0x8F4E;}
{_g_lq12VoltConSysa =0x8F50;}
{_g_lq12VoltConSysb =0x8F52;}
{_g_lq10CurrSampSysa =0x8F54;}
{_g_lq10CurrSampSysb =0x8F56;}
{_g_lq10CurrConSysa =0x8F58;}
{_g_lq10CurrConSysb =0x8F5A;}
{_g_lq10MdlCurr =0x8F5C;}
// {_g_lq10PowerConSysa =0x8F5C;}
// {_g_lq10PowerConSysb =0x8F5E;}
{_g_lq10MdlVoltUp =0x8F60;}
{_g_lq10ForceDriveFlg =0x8F62;}//????PFCo��DC����2����?��?�����̣���?2a��?
{_g_lq10BrdTstFlg =0x8F63;}//�̣���?2a��?,???��2a��?
{_g_lq10ReonTime =0x8F64;}
{_g_lq10OpenTime =0x8F66;}
{_g_lq10RunTime =0x8F68;}
{_g_lq10MaintainTimes =0x8F6A;}
{_g_lq10AcCurrFt =0x8F6C;}
{_g_lq10WalkInTime =0x8F6E;}
{_g_lq10MdlPowerFt =0x8F70;}
{_g_lq10SetPower =0x8F72;}
{_g_lq10MdlCurrFt =0x8F74;}
{_g_lq10SetLimit =0x8F76;}
{_g_lq10MdlVoltFt =0x8F78;}
{_g_lq10SetVolt =0x8F7A;}
{_g_u16MdlCtrl =0x8F7C;}
{_g_u16EpromWr =0x8F7D;}
{_g_u16BarCode0H =0x8F7E;}
{_g_u16BarCode0L =0x8F7F;}
{_g_u16BarCode1H =0x8F80;}
{_g_u16BarCode1L =0x8F81;}
{_g_u16BarCode2H =0x8F82;}
{_g_u16BarCode2L =0x8F83;}
{_g_u16BarCode3H =0x8F84;}
{_g_u16BarCode3L =0x8F85;}
{_g_u16MaintainData0H =0x8F86;}
{_g_u16MaintainData0L =0x8F87;}
{_g_u16MaintainData1H =0x8F88;}
{_g_u16MaintainData1L =0x8F89;}
{_g_u16CharactData0H =0x8F8A;}
{_g_u16CharactData0L =0x8F8B;}
{_g_u16NodeId0H =0x8F8C;}
{_g_u16NodeId0L =0x8F8D;}
{_g_u16NodeId1H =0x8F8E;}
{_g_u16NodeId1L =0x8F8F;}
{_g_u16VersionNoHw =0x8F90;}
{_g_lq10TempAmbiDisp =0x8F92;}
{_g_lq10DCTempUp =0x8F94;}
{_g_lq10PFCTempUp =0x8F96;}
{_g_lq10MdlVolt =0x8F98;}
{_g_u16MdlStatusH = 0x8F9A;}//XGH
{_g_lq10TempPFCDisp =0x8F9C;}
{_g_u16ACMAXPolarity =0x8F9E;}
{_g_lq10PFCCurrOffset =0x8FB0;}
{_g_lq10PFClooptstflag =0x8FB2;}
{_g_lq10shortflag =0x8FB3;}
{_g_lq10PfcVoltDisp =0x8FB4;}
{_g_u16VdcsetHVSDThreFlag =0x8FB6;}
{_g_i16DCPwmPermit =0x8FBA;}
{_g_u16ACOCPShortFlag =0x8FC1;} //Hexl20171225
/***************************************************************************/
{_Application_Entry_Point = 0x3F0000;}
{_ApplicationValidPointer = 0x3F7006;}
/*{_InitECanaIDPointer = 0x3F700A;}*/
{_SendBlockRequestPointer = 0x3F702E;}
{_GetHeaderPointer = 0x3F7030;}
{_GetDataBlockPointer = 0x3F7032;}
{_StartTimerPointer = 0x3F7034;}
{_TimeIsUpPointer = 0x3F7036;}
{_ProcessInquiryPointer = 0x3F7038;}
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
Howard,
As of now, I don't see any particular issue that can cause flash programmer to fail loading this.
1) Did they get any warnings when they compile the project? If yes, are they taken care or do they still exist?
2) Can you send the map file as well?
3) Generating debug server logs might help for further debug. You can generate the logs via "CCS Help menu -> CCS Support -> Select Debug Server Log -> Click on Properties -> Select Enable Debug Server Logging + Choose a log file location -> Click Ok". Please generate and share them.
4) Can you also select the "Enable Verbose Output" option provided at the bottom of the On-Chip Flash GUI in CCS (Tools menu -> On-Chip Flash)? Send us the console window output when it fails loading to Flash.
Please note: I will not be available until 27th. I will assign this post to my colleague to help you further.
Thanks and regards,
Vamsi
Howard,
I did not hear from you on this from the last 3 weeks. Do you have any update on this post?
Can I close this post?
Thanks and regards,
Vamsi