Communication between TMS320F28335-SPI-Master and TMS320F28335-SPI-Slave

Hi David,

David Kliewe said:

Uint16 data=0;

int main(void)

{

    Uint32 i=0;

    set_system_controls();

    init_pins_as_spi_master(0x0063);

    while (1){

        SPI_Send(0x8888);

        SPI_Read(&data);

    }

    return 0;

}

void SPI_Send(Uint16 data){

    TMC_BASE_SPIA->TXBUF=data;

    TMC_BASE_SPIA->FFTX |= (0x1<<6);    // Clear Interrupt Flag

}

void SPI_Read(Uint16 *data) {

    *data = TMC_BASE_SPIA->RXBUF;

    TMC_BASE_SPIA->FFRX |= (0x1<<6);    // Clear Interrupt Flag

}

The while(1) code in your master main code doesn't look right to me. You are continuously writing and reading from the SPI buffer without checking for status on each write and read. You are using FIFO, but at some point the CPU will overrun the FIFO. Similarly for RX, you are not checking to see if there is data ready before reading the register. I would advice you check the FIFO status bits before each write and read.

Hi Martinez,

Thank you for the quick response.

I changed my Send and Read function as shown here:

void SPI_Send(Uint16 data){
	if(TMC_BASE_SPIA->FFTX & 0x80){
		TMC_BASE_SPIA->FFTX |= (0x1<<6);	// Clear Interrupt Flag
		TMC_BASE_SPIA->TXBUF=data;
	}
}

void SPI_Read(Uint16 *data) {
	while(!(TMC_BASE_SPIA->FFRX & 0x80));
	TMC_BASE_SPIA->FFRX |= (0x1<<6);	// Clear Interrupt Flag
	*data = TMC_BASE_SPIA->RXBUF;
}

With these changes, I get a signal from slave to master that is --> 6x Master data  --> slave data --> master data --> slave data --> 6x master data --> etc etc...

In the debugger it seems to me as if TXFFINT (TMC_BASE_SPIA->FFTX & 0x80) is always high and never cleared....

I would be very thankful for some more hints.
Thanks in advance

David

Hi David,

dkl said:

In the debugger it seems to me as if TXFFINT (TMC_BASE_SPIA->FFTX & 0x80) is always high and never cleared....

The TXFFINT bit set if the FIFO status is less than the FIFO interrupt level. You will keep seeing that bit set unless you happen to read that bit right when the FIFO level is higher than the interrupt level. 

In any case, below is what I would recommend for your master writes and reads. Note that I'm using driverlib functions which are not supported for the device you are using, but still should give you a good idea. 

static inline void
SPI_writeDataBlockingFIFO(uint32_t base, uint16_t data)
{
    //
    // Check the arguments.
    //
    ASSERT(SPI_isBaseValid(base));

    //
    // Wait until space is available in the receive FIFO.
    //
    while(SPI_getTxFIFOStatus(base) == SPI_FIFO_TXFULL)
    {
    }

    //
    // Write data to the transmit buffer.
    //
    HWREGH(base + SPI_O_TXBUF) = data;
}

static inline uint16_t
SPI_readDataBlockingFIFO(uint32_t base)
{
    //
    // Check the arguments.
    //
    ASSERT(SPI_isBaseValid(base));

    //
    // Wait until data is available in the receive FIFO.
    //
    while(SPI_getRxFIFOStatus(base) == SPI_FIFO_RXEMPTY)
    {
    }

    //
    // Check for data to read.
    //
    return(HWREGH(base + SPI_O_RXBUF));
}

dkl said:

With these changes, I get a signal from slave to master that is --> 6x Master data  --> slave data --> master data --> slave data --> 6x master data --> etc etc...

Sorry, I don't understand what you mean here. However, can you restate your original problem? Is the sequence below what you expect?

MOSI: 0x8888 0x8888 0x8888 0x8888..

SOMI: 0xaaaa 0xbbbb 0xcccc 0xdddd..

But instead you are getting something like this?

MOSI: 0x8888 0x8888 0x8888 0x8888..

SOMI: 0xaaaa 0xaaaa 0xbbbb 0xbbbb..

Or do you want the SPI slave to simply echo the data received from the master?

A couple of points here:

1. The slave will always transmit something when there is a master clock. If the CPU on the slave side has not loaded the correct data in time, the slave will shift out whatever is in the SPIDAT register.
2. You have enabled TX FIFO mode on the slave side with a FIFO level of 8, so theoretically the SPI slave will have preloaded 8 characters before the master starts the SPI clock. This should mitigate (1) above, but not sure if this is what you want?
3. If you disable TX FIFO on the slave side, there is a short window (a race condition) for the CPU on the slave side to load data to the slave SPIDAT register given that the master is continuously transmitting data. It is technically possible to miss this deadline depending on CPU load. A delay between master data transmission gives the slave more time to be ready (careful to calculate this delay based on SPI clock cycles).

Let me understand your problem correctly and I can give you more suggestions.

Hi Martinez,
Thanks a lot for your time and your extensive replies.

I expect:

MOSI: 0x8888 0x8888 0x8888 0x8888..

SOMI: 0xaaaa 0xbbbb 0xcccc 0xdddd..

But instead I get

MOSI: 0x8888 0x8888 0x8888 0x8888 0x8888 0x8888..

SOMI: 0xaaaa 0x8888 0xbbbb 0x8888 0xcccc  0x8888..

I think you are right, that the slave has not enough time to load the correct data (and shifts out the SPIDAT register with data from master). But I still have no solution to provide the slave enough time for it. Also with delay between master data transmission I still get the same result....

Regards, David

Hi David,

I had incorrectly interpreted your code as having FIFO levels set to 8 (as stated in the code comments). However, I see the level set to 1. In your application, is it possible to set the FIFO level to a higher number? Specifically the slave TX FIFO level?

Hi Guz,

I changed the RX and TX FIFO level in slave to 0x8.

With these settings, the Slave TX interrupt is called exactly 4 times and then never again. That means, master data is on the MOSI and the MISO channel all the time...

RX and TX FIFO level in master is also set to 0x8

Hi David,

dkl said:

With these settings, the Slave TX interrupt is called exactly 4 times and then never again. That means, master data is on the MOSI and the MISO channel all the time...

I think this is because your ISRs are not taking into account that you have multiple characters in the RX FIFO and space for multiple characters in the TX FIFO. For example, the RX interrupt says you have 8 characters available, but you only read one. This is assuming you didn't modify your ISR code of course. 

Below is a snippet of the SPI interrupt example for F2833x in C2000Ware. In this example the RX/TX FIFO level is set to 8.

C:\ti\c2000\C2000Ware_3_02_00_00\device_support\f2833x\examples\spi_loopback_interrupts\Example_2833xSpi_FFDLB_int.c

//
// spiTxFifoIsr -
//
__interrupt void 
spiTxFifoIsr(void)
{
    Uint16 i;
    for(i=0;i<8;i++)
    {
       SpiaRegs.SPITXBUF=sdata[i];      // Send data
    }

    for(i=0;i<8;i++)                    // Increment data for next cycle
    {
        sdata[i] = sdata[i]+ 1;
    }

    SpiaRegs.SPIFFTX.bit.TXFFINTCLR=1;  // Clear Interrupt flag
    PieCtrlRegs.PIEACK.all|=0x20;  		// Issue PIE ACK
}

//
// spiRxFifoIsr - 
//
__interrupt void 
spiRxFifoIsr(void)
{
    Uint16 i;
    for(i=0;i<8;i++)
    {
        rdata[i]=SpiaRegs.SPIRXBUF;		// Read data
    }
    
    for(i=0;i<8;i++)                    // Check received data
    {
        if(rdata[i] != rdata_point+i)
        {
            error();
        }
    }
    rdata_point++;
    SpiaRegs.SPIFFRX.bit.RXFFOVFCLR=1;  // Clear Overflow flag
    SpiaRegs.SPIFFRX.bit.RXFFINTCLR=1; 	// Clear Interrupt flag
   

Hi Gus,

thank you for your endurance!

With the code from example, I still get some of master data sent back to master...

Here is my current configuration on master:

Uint16 sdata[8];     // Send data buffer
Uint16 rdata[8];     // Receive data buffer
int main(void)
{
	Uint32 i=0, c=0;

    for(i=0;i<8;i++)
    {
    	sdata[i]=0x8888;      // Configure send data
    }

	set_system_controls();
	init_pins_as_spi_master(GPIO16, GPIO17, GPIO18, GPIO19, 16, 1500000);	//wordlength: 16 bit, baudrate: 1.5 MHz
	while(1){
		SPI_Send(&sdata[0]);
		SPI_Read(&rdata[0]);
	}

	return 0;
}

init master{


	//Set in Reset
	TMC_BASE_SPIA->CCR &= ~(0x1<<7);

	// Enable master mode, normal phase, enable talk, and SPI int disabled.
	TMC_BASE_SPIA->CTL |= 0x0004;	//Enable master mode
	TMC_BASE_SPIA->CTL |= 0x0002;	//Enable  transmission
	//TMC_BASE_SPIA->CTL |= 0x0001;	//Enable interrupts
	TMC_BASE_SPIA->BRR |= (F_LSPCLK/baudrate)-1;
	TMC_BASE_SPIA->CCR |= wordlength_in_bit-1;

	// Initialize SPI FIFO registers
	TMC_BASE_SPIA->FFRX &= ~(0x1F);		// Receive
	TMC_BASE_SPIA->FFRX |= (0x8);		// // Set RX FIFO level to 1
	TMC_BASE_SPIA->FFRX |= (0x1<<5);	// Enable interrupt
	TMC_BASE_SPIA->FFRX |= (0x1<<6);	// Clear Interrupt Flag
	TMC_BASE_SPIA->FFRX |= (0x1<<13);	// Re-enable receive FIFO operation

	TMC_BASE_SPIA->FFTX |= (0x8);		// Set TX FIFO level to 1
	//TMC_BASE_SPIA->FFTX |= (0x1<<5);	// Enable Interrupt
	TMC_BASE_SPIA->FFTX |= (0x1<<6);	// Clear Interrupt Flag
	TMC_BASE_SPIA->FFTX |= (0x1<<13);	// Release FIFO from reset
	TMC_BASE_SPIA->FFTX |= (0x1<<14);	// FIFO enhancements enabled
	TMC_BASE_SPIA->FFTX |= ((Uint32)0x1<<15);	// SPI FIFO resume

	//Out of Reset
	TMC_BASE_SPIA->CCR |= (0x1<<7);   // Relinquish SPI from Reset and set char length
}

Here is my configuration on slave:

__interrupt void spiRxFIFOISR(void);
__interrupt void spiTxFIFOISR(void);



Uint16 sdata[8];     // Send data buffer
Uint16 rdata[8];     // Receive data buffer
int main(void)
{
	Uint16 i=0;

    for(i=0;i<8;i++)
    {
    	sdata[i]=0xF0F0;      // Configure send data
    }

	set_system_controls();
	init_pins_as_spi_slave(GPIO16, GPIO17, GPIO18, GPIO19, 16);	//wordlength: 16
        SPI_set_Interrupt_RX(&spiRxFIFOISR);
        SPI_set_Interrupt_TX(&spiTxFIFOISR);
	while(1){

	}

	return 0;
}

__interrupt void spiRxFIFOISR(void){
	SPI_Read(&sdata[0]);
	interrupt_ack_spi();

}
__interrupt void spiTxFIFOISR(void){
	SPI_Send(&rdata[0]);
	interrupt_ack_spi();
}

init slave{
//Set in Reset
	TMC_BASE_SPIA->CCR &= ~(0x1<<7);

	// Enable slave
	TMC_BASE_SPIA->CTL &= ~(0x0004);	//disable master mode
	TMC_BASE_SPIA->CTL |= (0x2);		//Enable transmission
	TMC_BASE_SPIA->CTL |= (0x1);	//Enable interrupts
	TMC_BASE_SPIA->CCR |= wordlength_in_bit-1;


	// Initialize SPI FIFO registers
	TMC_BASE_SPIA->FFRX &= ~(0x1F);		// Receive
	TMC_BASE_SPIA->FFRX |= (0x8);		// // Set RX FIFO level to 8
	TMC_BASE_SPIA->FFRX |= (0x1<<5);	// Enable interrupt
	TMC_BASE_SPIA->FFRX |= (0x1<<6);	// Clear Interrupt Flag
	TMC_BASE_SPIA->FFRX |= (0x1<<13);	// Re-enable receive FIFO operation

	TMC_BASE_SPIA->FFTX |= (0x1<<13);	// Release FIFO from reset
	TMC_BASE_SPIA->FFTX |= (0x1<<14);	// FIFO enhancements enabled
	TMC_BASE_SPIA->FFTX |= (0x8);		// Set TX FIFO level to 8
	TMC_BASE_SPIA->FFTX |= (0x1<<5);	// Enable Interrupt
	TMC_BASE_SPIA->FFTX |= (0x1<<6);	// Clear Interrupt Flag
	TMC_BASE_SPIA->FFTX |= ((Uint32)0x1<<15);	// SPI FIFO resume

	//Out of Reset
	TMC_BASE_SPIA->CCR |= 0x0080;   // Relinquish SPI from Reset and set char length

	return 0;
}

here are my functions

void SPI_Send(Uint16 *sdata){

    Uint16 i;
    for(i=0;i<8;i++)
    {
    	TMC_BASE_SPIA->TXBUF=sdata[i];      // Send data
    }

    TMC_BASE_SPIA->FFTX |= (0x1<<6);	// Clear Interrupt Flag

}

void SPI_Read(Uint16 *rdata) {

	Uint16 i;
	for(i=0;i<8;i++)
	{
		rdata[i]=TMC_BASE_SPIA->RXBUF;		// Read data
	}

	TMC_BASE_SPIA->FFRX |= (0x1<<14);	// Clear Overflow Flag
	TMC_BASE_SPIA->FFRX |= (0x1<<6);	// Clear Interrupt Flag

}

Feels like I almost tried everything now, but I always get some master-data back on somi line ...
Thank you very much for your help.

Regards,
David

David,

Looking at your slave code, I see you initialize sdata buffer and keep rdata uninitialized. Then for your TX ISR you send rdata, is this right? For the RX ISR, you save your received data in sdata.

Gus Martinez said:

David,

Looking at your slave code, I see you initialize sdata buffer and keep rdata uninitialized. Then for your TX ISR you send rdata, is this right? For the RX ISR, you save your received data in sdata.

Hi Guz,

Because I am running slave and master on two different machines, I just typed my code from the slave machine viay keyboard into this forum and and made mistake there. 

My code on my slave machine is:

Uint16 sdata[8];
Uint16 rdata[8];
int main(void)
{
	Uint16 i=0;
	for(i=0;i<8;i++){
		sdata[i]=0xF0F0;
	}
	set_system_controls();
	init_pins_as_spi_slave(GPIO16, GPIO17, GPIO18, GPIO19, 16);
	SPI_set_Interrupt_RX(&spiRxFIFOISR);
	SPI_set_Interrupt_TX(&spiTxFIFOISR);

	while(1){

	}
	return 0;
}

__interrupt void spiRxFIFOISR(void){
	SPI_Read(&rdata[0]);
	interrupt_ack_spi();
}

__interrupt void spiTxFIFOISR(void){
	SPI_Send(&sdata[0]);
	interrupt_ack_spi();
}

Hi Gus,

Acutally it is 

Uint16 sdata[8];
Uint16 rdata[8];
int main(void)
{
	Uint16 i=0;
	for(i=0;i<8;i++){
		sdata[i]=0xF0F0;
	}
	set_system_controls();
	init_pins_as_spi_slave(GPIO16, GPIO17, GPIO18, GPIO19, 16);
	SPI_set_Interrupt_RX(&spiRxFIFOISR);
	SPI_set_Interrupt_TX(&spiTxFIFOISR);

	while(1){

	}
	return 0;
}

__interrupt void spiRxFIFOISR(void){
	SPI_Read(&rdata[0]);
	interrupt_ack_spi();
}

__interrupt void spiTxFIFOISR(void){
	SPI_Send(&sdata[0]);
	interrupt_ack_spi();
}

I made a mistake by typing it into forum... 

Regards, David

Hi David,

OK, I'm not quite sure what could be going on. Can you provide any additional information? For example, at time zero does the master SPI start transmitting while the slave SPI is booting up? Or do you have some mechanism (GPIO?) to ensure the slave SPI is ready before the master starts? Is the CPU on the slave device servicing any other interrupts along with the SPI slave TX interrupts? Does the MISO data look ok at the beginning of the transfers and start failing later?

One suggestion I can make is to use the FFTXDLY bits in the SPIFFCT register in the *master* code. These bits add a delay between word transfers. Maybe this can help you avoid the issue?

Another suggestion is to change the TX ISR on the slave side. Instead of writing only 8 characters, fill up the FIFO completely. You can write to the TX FIFO until TXFFST=10h in the SPIFFTX register.