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TMS320F280049C: DriverLib PLL Configuration Delay

Part Number: TMS320F280049C


In the DriverLib file, sysctl,.c, there is a delay added in the PLL configuration.  There is no reference to this delay in the TRM/Docs.

                    //

                    // Turn off PLL

                    //

                    EALLOW;

                    HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLCTL1) &=

                        ~SYSCTL_SYSPLLCTL1_PLLEN;

 

                    SysCtl_delay(3U);

 

                    //

                    // Write multiplier, which automatically turns on the PLL

                    //

                    HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLMULT) = pllMult;

Also, no code comment explaining.  Can you please provide details on this delay?

Thanks,

Eric

  • Hi Eric,

    PLL power down signal goes through clock domain crossing, and hence goes through synchronizers in the path. This delay is added to account for synchronization to ensure PLL powers down before powering up with different PLL multiplier settings (which is the next instruction).

    Regards,

    Nirav