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TMS320F28379D: SCI UART communication - Distinguishing data Frames

Part Number: TMS320F28379D

Hello,

I am working with the SCI/UART in asynchronous mode. I am continuously transmitting three 16 bit frames (with two 8 bit data packets) . The problem that I encounter is that some packets get lost in the process and the data in the frame thus gets misplaced. How can I work around this issue ?

Also, I do not want to use the idle line mode as the idle bits will significantly delay my communication loop. Use of address bit mode is still a choice but is there a good example to refer too and also is there a way to work around this without the need for the idle line mode or the address bit mode.

Thanks & Regards,

Radha

  • Hi Radha,

    Thanks for your question. As you mentioned, the packets should not be lost in transmission, unless there is collision happening between data packets, or there is insufficient differentiation between idle time and bits.

    The best way to handle this will indeed be use of the address-bit mode, but depending on how high-speed the baud rate is, a 10 bit idle may still be unavoidable in the transmission stream.

    While there are currently no examples directly utilizing this, the description in section 19.9.1 (Sending an Address) of the TRM should provide an excellent starting place for utilizing address-bit mode.

    Regards,

    Vince

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  • Hello Vince,

    Appreciate your prompt response. 

    I am targeting baud rates closer to 4 ~ 6.25 Mbps. With this baud rate, do we still need to have idle bits in the transmission stream in address bit mode. My understanding is if we operate in address bit mode, the idle period is of no significance.

    Also, I am only thinking of the address packet as a means to distinguish between the data frames and give a definite structure to the frame. Is there a possibility of collision or corruption of data despite using the address bit mode.

    Thanks & Regards,

    Radha

  • Hi Radha,

    Thanks for the follow up questions! Please see responses below:

    Q1

    I am targeting baud rates closer to 4 ~ 6.25 Mbps. With this baud rate, do we still need to have idle bits in the transmission stream in address bit mode. My understanding is if we operate in address bit mode, the idle period is of no significance.

    While the idle period is of no significance, in address-bit mode specifically at high speeds, the program itself has issues keeping up with the frames (see below quote from the "Recognizing the Address Byte" section of the TRM):

    The address-bit mode (Section 19.9) adds an extra bit (that is, an address bit) into every byte to distinguish addresses from data. This mode is more efficient in handling many small blocks of data because, unlike the idle mode, it does not have to wait between blocks of data. However, at a high transmit speed, the program is not fast enough to avoid a 10-bit idle in the transmission stream.

    Q2

    Also, I am only thinking of the address packet as a means to distinguish between the data frames and give a definite structure to the frame. Is there a possibility of collision or corruption of data despite using the address bit mode.

    There is still possibility of collision/corruption -if- the data received is actually unreadable according to the receiver signal format of a frame. Basically stated, if the C2000 receives byte/frames that do not have proper timing for the bits to be determined as 1/0, then corruption of the frame can occur. The image below from section 19.10 of the TRM shows how our device strobes each bit and determines the 1/0 state, as well as the start bit detection:

    So unfortunately, considering the application mentioned here is approaching the upper baud-rate limits of the device, the speed of the program will likely require an idle-time of 10 bits as mentioned in the TRM.

    Let me know if you have any additional questions regarding this, or if we can help debug further!

    Regards,

    Vince

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  • Hello Vince,

    Thank you so much for the reply. I will enable the address bit mode and get back to you in case I have more questions.

    I have a follow up question on SCI though. I am working with three SCI peripherals at any instant. Can SCI A-D operate in parallel. For instance, can I transmit/receive through both SCI A and B at any instant without any issues ?

    Thanks & Regards,

    Radha

  • Hi Radha,

    Thanks for your question. Just as a note for the future, please place new questions in a new thread, as it allows other customers to more easily find the answer when they search for it!

    To answer the question, yes, with a dual-core device, you can operate two instances of SCI in parallel. However, I would suggest that in most cases, it would be simpler and more efficient to use one CPU and simply utilize the FIFOs in SCI on the two ports. Utilizing a CPU core for each SCI would likely be a bit excessive for most circumstances, unless very high through-put is required. See the following similar question:

    https://e2e.ti.com/support/microcontrollers/c2000/f/171/t/697332?TMS320F28379D-How-many-diffrent-processes-can-be-run-in-parallel-Is-it-possible-to-run-2-SPI-communications-and-a-UART-interface-to-PC-in-parallel-simultaneously-

    Regards,

    Vince

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    If I was able to answer your question, please press the green "Verified" button below, thanks!

  • Hello Vince,

    Thank you Vince.

    Regards,

    Radha