• State TI Thinks Resolved
  • Locked Locked
  • Replies 6 replies
  • Answers 2 answers
  • Subscribers 82 subscribers
  • Views 367 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F28377S: TMS320F28377S A/D data offset

kevin.huang_FJXM
Expert 2925 points

Part Number: TMS320F28377S

When the module is found to be abnormal, it is the following working parameters:

Input voltage: 157 ~ 162vdc;

High end output voltage Vc1: 70V;

The output voltage vc2 of low-end regulation is 40V;

Total output voltage Vout: 30VDC;

Module adjustment frequency: 50KHz, DSP real-time AD acquisition frequency 40K, configuration S + h time is more than 320ns;

A / D reference voltage is 2.5V, differential 16 bit resolution;

A / D design Description:

Vc1 sampling differential input pin: adcinb0 (+) and adcinb1 (-), input voltage of the pin: 70 / 100 = 700mV;

Vc2 sampling differential input pin: adcinb2 (+) and adcinb3 (-), the input voltage of the pin is 40 / 30 = 1333mv;

 

Fault phenomenon:

1) When the equipment is started, the output voltage Vc1 will slowly shift to one side, up to 2V (most of them are positive bias), which is the same regardless of on load or no-load conditions, resulting in the total output deviation from the output requirements, and the module can not work normally.

2) At this time, the output voltage vc2 is stable. At the same time, other a / D circuits of DSP are normal. At the same time, the voltage of a / D sampling pin of DSP chip is monitored, and there is no obvious deviation phenomenon.

3) During the test, it is found that the general module can enter the stable state after 10 minutes of startup, and the Vc1 voltage will not continue to shift.

4) If the voltage output is stable and restart immediately, generally there will be no offset phenomenon. If the machine is started again after sufficient shutdown time, the phenomenon still exists.

4) If the two groups of voltage sampling pins (Vc1 and vc2) are switched on DSP (the program also switches the sampling channels), the voltage offset will shift to vc2 and Vc1 will become stable.

Improve the test phenomenon:

5) Change the two poles (voltage Vc1) of differential sampling input to DSP to adcin14 (+) and adcin15 (-), and disconnect adcinb0 (+) and adcinb1 (-). The voltage of Vc1 can be stably output. (if it is not turned on, the output voltage offset will appear on vc2, while the output voltage of Vc1 is stable);

 

After the above, we speculate that: because of the interference between the A / D sampling channels of f28377s, there will be A/D data offset, and then cause the module control error deviation, abnormal!

Please professional analysis of the exception, provide solutions!

At present, 3 ~ 5 sets of equipment have been transformed manually, and the control accuracy deviation of output voltage is within 30mV after testing.

Attached: DSP peripheral pair sampling related circuit schematic diagram:

  • 0 in reply to kevin.huang_FJXM
    TI__Guru 62975 points

    Kevin,

    Based on the schematic, it looks like the negative reference of the 16-b ADC differential pairs are biased to GND_A, which will not satisfy the common mode voltage requirements for the 16-b differential mode:

    One potential explanation for why B0+B1 might behave differently from 14+15 would be the parasitic capacitance characteristics:

    -Tommy

  • 0 in reply to tlee
    Expert 2925 points

    According to the second point mentioned by Tommy, we have made experiments:

    1) When the input line of AD sampling is unchanged, the total output is still 30V when Vc1 = 60V and Vc1 = 30V (that is, the input to adcinb0 / 1 port is reduced to 600mV, and the input to adcinb2 / 3 port is reduced to 1000mV), the total output is still 30V. The present image still exists.

    2) We have removed, reduced and increased the input to the adcinb0 port filter capacitance test, there is no significant improvement, the image still exists.

  • 0 in reply to kevin.huang_FJXM
    TI__Guru 62975 points

    Kevin,

    Can you clarify the observed failure rate?  For example: a) this is affecting all systems from a prototype build that is still under development, or b) this is a new failure for a design that has been in production for two years.

    -Tommy

  • 0 in reply to tlee
    Prodigy 10 points

    this is a new failure for the design ,

    There was no problem last year, and it was occurred only after May this year.

  • 0 in reply to Zhang Ming
    TI__Guru 60865 points

    Hi Kevin and Zhang,

    Can you address Tommy's first question: Is the input  fully differential as required in the datasheet operating conditions, or has the negative input been connected to ground?  If it is the second case, the ADC is not expected to function in these circumstances and the output results produced will be undefined.  Without revising the board, it would be recommended to switch to 12-bit single-ended in this case.

    For the ADC driving circuit, what is the total source resistance and capacitance and what is the driving amplifier bandwidth? What have you configured the S+H duration to? It looks like the amplifier BW is 7MHz, there are 2 x 1kohm series resistors, and 2 x unlabeled capacitors? The 2kohm series resistance is probably going to be a problem as you'll have trouble settling the ADC input to 16-bits (or possibly even 12-bits) during the S+H time.  See:

      

    for information on how to evaluate the ADC input settling performance.  

    For the VREFHI pins, it looks like you have a 5-ohm series resistor in the VREFHI path?  This would not be recommended.  If you need to stabilize the VREFHI driving op-amp due to the large capacitive load on the VREFHI pin, you'll want to put a snubbing resistor in series with capacitor (as shown in the TRM section "Designing an External Reference Circuit") as opposed to in series with the reference path.  This is to ensure that the variable current drawn by the reference doesn't cause a variable I-R drop across the resistor, resulting in distortion due to changing VREFHI voltage.  Another useful reference for this would be the TI Precision labs video series here: