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I tried to trigger the CLA task via software trigger feature but it is not working.
1. I used .cmd file given in the c2000 folder named as "2837xD_RAM_CLA_Ink_cpu1.cmd"
2. I enabled the clock for CLA.
3. In main function I used Pragma for using a variable .cla file
#pragma DATA_SECTION (CLAMEMORY,"Cla1ToCpuMsgRAM");
4. I Created a .cla file in which I assigned a value to the variable as follows
__interrupt void Cla1Task1(void) { __mdebugstop(); CLAMEMORY=2; }
5. I initialized the following registers for CLA
asm(" EALLOW"); MemCfgRegs.LSxMSEL.bit.MSEL_LS0 = 1; // 0=CPU 1=CPU and CLA MemCfgRegs.LSxMSEL.bit.MSEL_LS1 = 1; // 0=CPU 1=CPU and CLA MemCfgRegs.LSxMSEL.bit.MSEL_LS2 = 1; // 0=CPU 1=CPU and CLA MemCfgRegs.LSxMSEL.bit.MSEL_LS3 = 0; // 0=CPU 1=CPU and CLA MemCfgRegs.LSxMSEL.bit.MSEL_LS4 = 1; // 0=CPU 1=CPU and CLA MemCfgRegs.LSxMSEL.bit.MSEL_LS5 = 0; // 0=CPU 1=CPU and CLA MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS0 = 0; // 0=CLA data memory 1=CLA program memory MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS1 = 0; // 0=CLA data memory 1=CLA program memory MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS2 = 0; // 0=CLA data memory 1=CLA program memory MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS3 = 0; // 0=CLA data memory 1=CLA program memory MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS4 = 1; // 0=CLA data memory 1=CLA program memory MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS5 = 0; // 0=CLA data memory 1=CLA program memory Cla1Regs.MVECT1 = (uint16_t)(&Cla1Task1); DmaClaSrcSelRegs.CLA1TASKSRCSEL1.bit.TASK1 = 0; // 0=none/software DmaClaSrcSelRegs.CLA1TASKSRCSELLOCK.bit.CLA1TASKSRCSEL1 = 0; // Write a 1 to lock (cannot be cleared once set) DmaClaSrcSelRegs.CLA1TASKSRCSELLOCK.bit.CLA1TASKSRCSEL2 = 0; // Write a 1 to lock (cannot be cleared once set) asm(" EDIS");
6. I used the following registers for triggering "Cla1Task1" via software trigger
Cla1Regs.MIER.all = 0x0001; // Enable CLA interrupt 1 Cla1Regs.MCTL.bit.IACKE = 0x0001; // Enable IACKE to start task using software (0x0001---> for task 1)
7. I am not enabling any CLA interrupt to be enabled after processing the CLA task Hence I didn't use the PieCtrlRegs.
8. I ran the code and did the following during debugging,
9. Now my Question is
Thank you waiting for your reply
Hello,
Please compare your code to one of the working examples in C2000Ware.
For instance, C:\ti\c2000\C2000Ware_3_03_00_00\device_support\f2837xd\examples\cpu1\cla_divide\cpu01
I scanned the code above and the only thing I have to suggest is #6 the write to MIER may require EALLOW protection to be disabled.
Regards
Lori
1. Which of the following is used for software trigger ?
Cla1Regs.MCTL.bit.IACKE = 0x0001; Cla1Regs.MIFRC.bit.INT1 = 1;
2. Does Cpu2 have separate CLA? (Because they have mentioned two CLA in datasheet)
3. Is Configuring CLA1 to either CPU1 or CPU2 possible?
4. Can I use both CLA's (CLA1_CPU1 and CLA1_CPU2) simultaneously in parallel?
Ganeshapandi K said:1. Which of the following is used for software trigger ?
12Cla1Regs.MCTL.bit.IACKE = 0x0001;
Cla1Regs.MIFRC.bit.INT1 = 1;
Ganeshapandi,
In the divide example I mentioned:
Also refer to this FAQ: https://software-dl.ti.com/C2000/docs/cla_software_dev_guide/debugging.html#why-can-t-i-force-a-task-using-software-iack
Ganeshapandi K said:2. Does Cpu2 have separate CLA? (Because they have mentioned two CLA in datasheet)
Refer to the functional block diagram in the datasheet. It shows which peripherals (and CLA) is attached to each CPU.
Ganeshapandi K said:3. Is Configuring CLA1 to either CPU1 or CPU2 possible?
No, refer to the functional block diagram.
Ganeshapandi K said:4. Can I use both CLA's (CLA1_CPU1 and CLA1_CPU2) simultaneously in parallel?
Yes, they are independent blocks as shown in the functional block diagram.