CCS/TMS320F28377D: CMPSS comparator latch outputs won't clear

Tool/software: Code Composer Studio

I am trying to configure the comparator subsystem for ePWM trip based on some measured signals. I would like to use the latched outputs of the low and high comparators for the trip rather than using directly the digital filter output. There are two reasons why I would like to use the latched output:

1) The latched output does not automatically reset so there are no endless cycles of PWM enable-disable because the latched output will stay, well, latched.

2) I would like the ePWM to stay tripped until the user resets it after acknowledging a fault (for example an overcurrent).

Before writing code for fault flag generation, I wanted to check if the latched outputs behaved the way they were described in the Technical Reference Manual. I found that for the low-comparator the COMPLLATCH does not clear (to zero) even if I write 1 to LLATCHCLR during initialization, while for the high-comparator, COMPHLATCH does initialize to zero with HLATCHCLR set to 1 during initialization. The other problem I come across is not being able to reset either COMPHLATCH or COMPLLATCH through software by writing 1 to HLATCHCLR and LLATCHCLR, respectively.

The initialization code is pasted below. Please do note that the setting for CTRIPOUTHSEL and CTRIPHSEL (and also for the low-comparator) is set as 2 in the following code because I haven't changed the trip to latched output yet. I'm currently just testing the latched outputs by visualizing them.

Any help will be much appreciated.

void InitCMPSS1(void)
{
	// Initialise CMPSS1 (ADCINA2/CMPIN1P)

	EALLOW;
	// Comparator Control Register
	Cmpss1Regs.COMPCTL.bit.COMPDACE = 1;			// Enable Comparator/DAC
	Cmpss1Regs.COMPCTL.bit.ASYNCLEN = 0;			// Async comp output does not OR with latched digital filter output
	Cmpss1Regs.COMPCTL.bit.COMPLINV = 1;			// Output of low comparator is inverted
	Cmpss1Regs.COMPCTL.bit.COMPLSOURCE = 0;			// Inverting input of comparator driven by internal DAC
	Cmpss1Regs.COMPCTL.bit.ASYNCHEN = 0;			// Async comp output does not OR with latched digital filter output
	Cmpss1Regs.COMPCTL.bit.COMPHINV = 0;			// Output of high comparator is NOT inverted
	Cmpss1Regs.COMPCTL.bit.COMPHSOURCE = 0;			// Inverting input of comparator driven by internal DAC

	// Comparator Hysteresis Control Register
	Cmpss1Regs.COMPHYSCTL.bit.COMPHYS = 1;			// Set to TYPICAL hysteresis

	// High DAC Value Shadow Register
	Cmpss1Regs.DACHVALS.bit.DACVAL = TRIPLEVELHI;	// High DAC shadow threshold (90% of 4095)

	// Low DAC Value Shadow Register
	Cmpss1Regs.DACLVALS.bit.DACVAL = TRIPLEVELLO;	// Low DAC shadow threshold (10% of 4095)

	// Low Filter Control Register
	Cmpss1Regs.CTRIPLFILCTL.bit.SAMPWIN = 9;		// Filter sample window size
	Cmpss1Regs.CTRIPLFILCTL.bit.THRESH = 5;			// Filter majority voting threshold
	Cmpss1Regs.CTRIPLFILCLKCTL.bit.CLKPRESCALE = 1;	// Filter sample clock = SYSCLK
	Cmpss1Regs.CTRIPLFILCTL.bit.FILINIT = 1;		// Initialize all samples to filter input

	// High Filter Control Register
	Cmpss1Regs.CTRIPHFILCTL.bit.SAMPWIN = 9;		// Filter sample window size
	Cmpss1Regs.CTRIPHFILCTL.bit.THRESH = 5;			// Filter majority voting threshold
	Cmpss1Regs.CTRIPHFILCLKCTL.bit.CLKPRESCALE = 1;	// Filter sample clock = SYSCLK
	Cmpss1Regs.CTRIPHFILCTL.bit.FILINIT = 1;		// Initialize all samples to filter input

	// Set output signal paths
	Cmpss1Regs.COMPCTL.bit.CTRIPOUTHSEL = 2;		// Filter output drives CTRIPOUTH
	Cmpss1Regs.COMPCTL.bit.CTRIPOUTLSEL = 2;		// Filter output drives CTRIPOUTL
	Cmpss1Regs.COMPCTL.bit.CTRIPHSEL = 2;			// Filter output drives CTRIPH
	Cmpss1Regs.COMPCTL.bit.CTRIPLSEL = 2;			// Filter output drives CTRIPL

	// Reset output latch of digital filter
    Cmpss1Regs.COMPSTSCLR.bit.HLATCHCLR = 1;
    Cmpss1Regs.COMPSTSCLR.bit.LLATCHCLR = 1;

	EDIS;
}