Tool/software: Code Composer Studio
The TMS320F28375D specification states that the PWM frequency is MAX 100MHz,
but it looks like it is operating at 200Mhz with the following settings.
Is this out of warranty, or is it my misunderstanding?
==============================================================================
EALLOW;
ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV = 0x0; // 0 = /1. 1 = /2.
EDIS;
// To SHARC1 PWM.
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count updown
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
EPwm1Regs.TBPRD = 25; // Set timer period
EPwm1Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter
// Setup shadow register load on ZERO
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Set Compare values
EPwm1Regs.CMPA.bit.CMPA = 0; // Set compare A value
EPwm1Regs.CMPB.bit.CMPB = 0; // Set Compare B value
// Set actions A(Upper)
EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET; // Set PWM1A on Zero
EPwm1Regs.AQCTLA.bit.PRD = AQ_CLEAR; // Clear PWM1A on period
EPwm1Regs.AQCTLA.bit.CAU = AQ_NO_ACTION; // Nothing
EPwm1Regs.AQCTLA.bit.CAD = AQ_NO_ACTION; // Nothing
EPwm1Regs.AQCTLA.bit.CBU = AQ_NO_ACTION; // Nothing
EPwm1Regs.AQCTLA.bit.CBD = AQ_NO_ACTION; // Nothing
// Set actions B(Lower)
EPwm1Regs.AQCTLB.bit.ZRO = AQ_SET; // Set PWM1B on Zero
EPwm1Regs.AQCTLB.bit.PRD = AQ_CLEAR; // Clear PWM1B on period
EPwm1Regs.AQCTLB.bit.CAU = AQ_NO_ACTION; // Nothing
EPwm1Regs.AQCTLB.bit.CAD = AQ_NO_ACTION; // Nothing
EPwm1Regs.AQCTLB.bit.CBU = AQ_NO_ACTION; // Nothing
EPwm1Regs.AQCTLB.bit.CBD = AQ_NO_ACTION; // Nothing
// Set Other
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // Enable DeadBand
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Inversion AQOUTB
EPwm1Regs.DBCTL.bit.IN_MODE = DBA_RED_DBB_FED;// (AQOUTA:RED AQOUTB:FED)
EPwm1Regs.DBCTL.bit.HALFCYCLE = 0;
EPwm1Regs.DBRED.bit.DBRED = 1; // Upper Dead time
EPwm1Regs.DBFED.bit.DBFED = 1; // Lower Dead time
// Interrupt where we will change the Compare Values
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_PRD; // Select INT on PRD event.
EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm1Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st
EPwm1Regs.ETCLR.bit.INT = 1; // INT flg clear
=================================================================================
Sorry Oscilloscope images cannot be placed,
but the time from one Rising Edge to the next Rising Edge is 250nsec.
250ns = 25(PRD) * 2(UP/DOWN) * 5ns
point out if you make a mistake.
Thanks and regards.