TMS320F280049: F280049 PLL errata question.

Huihuang Chen

Part Number: TMS320F280049
Other Parts Discussed in Thread: C2000WARE

Hi Champ,

I see the f28004x_sysctrl.c file which under " C2000Ware_3_01_00_00\device_support\f28004x\common\source" folder has following code:

after ClkCfgRegs.SYSPLLCTL1.bit.PLLEN = 0, just 33 cycles delay.

But from the TRM ,At least 60 CPU clock cycles delay is needed after PLL is powered down,

Could you advise 33 cycles is reasonable or not?

It is seems the IsPLLValid(Uint16 oscSource, Uint16 imult, Uint16 fmult) function didn't implement DCC: Single-Shot-Mode Operation May End Prematurely workaround? could you advise my understanding is correct or not?

over 4 years ago

0 Veena Kamath over 4 years ago

TI__Mastermind 32565 points

Hi Huihuang Chen,

Thanks for reporting this. I believe the correct delay should be 60 NOPs. I will raise a ticket to get this fixed in the next release.

I will also a change request to the isPLLvalid to include the errata workaround

Regards,

Veena

0 Huihuang Chen over 4 years ago in reply to Veena Kamath

TI__Expert 4050 points

Hi Veena,

i found it is 60 cycles in C2000Ware_2_00_00_0, may i know the reason to change to 30?

for(retries = 0; (retries < PLL_RETRIES); retries++)
{
//
// Bypass PLL
//
ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 0;

//
// Delay of at least 60 OSCCLK cycles required post PLL bypass
//
asm(" RPT #60 || NOP");

0 Veena Kamath over 4 years ago in reply to Huihuang Chen

TI__Mastermind 32565 points

Hi Huihuang Chen,

This code is setting the PLLCLKEN register bit, whereas the 3.x code is setting the PLLEN bit. PLLCLKEN register write is always followed by 60 NOPs. I believe we need to correct the number of NOPs required after PLLEN bit as well to 60.

Regards,

Veena

0 Huihuang Chen over 4 years ago in reply to Veena Kamath

TI__Expert 4050 points

HI Veena,

Noted and thanks!

So right way is setting PLLCLKEN or PLLEN ?

What is our suggestion?

0 Veena Kamath over 4 years ago in reply to Huihuang Chen

TI__Mastermind 32565 points

Hi Huihuang Chen,

The 2.x code was just bypassing the PLL. The updated code disables the PLL. It should be PLLEN.

Regards,

Veena

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TMS320F280049: F280049 PLL errata question.