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TMS320F280041: ADC interrupt timing problem.

user6089296
Prodigy 40 points
Part Number: TMS320F280041

Hi All,

I' am using F280041 for peak current mode application,

There are 2 group adc in the system, first is ADCA   for current measurement, second is ADCC for voltages and temperatures. I want to start adc sample by triggering PWM1 compare A and B register.  When i set CMPA = 0  , i see that interrupt time is more around  300 ns than i calculated value. My setting like below.

Prescale value = 0; 

Sample time = 2; 

ADCA  = { SOC0 = A1; SOC1 = A1; SOC2= A2; SOC3 = A2 }

ADCC  = { SOC0 = C1; SOC1 = C2; SOC2= C3; SOC3 = C4 }

Total s&H time should be : (((11+3) * 4) + 1) * 10ns = 570ns, but i see 870 ns on the scope. (i am using gpio6 to see intterrupt timing on the scope)

when i change CMPA = 50 , i see 1370 ns on the scope. 

How can i solve it ?

  • 0
    TI__Guru 60865 points

    Hi '9296

    See the "ADC Timing Diagrams" section of the device datasheet and the "ADC Operating Conditions" table, also in the datasheet. 

    Assuming SYSCLK = 100MHz, ADCCLK = 50MHz, ACQPS = 7 then each conversion will take (ACQPS + 1) SYSCLK cycles for the S+H and Teoc cycles for the conversion = 21 SYSCLK cycles for a total of 28 cycles per conversion.

    There is also a trigger to first S+H latency of 2 cycles.

    So, assuming late interrupt mode, the ADCINT will get triggered after 2 + 4*(8 + 21) = 118 cycles (1180ns)

    This doesn't include the context switch latency for the CPU to enter an ISR or time for the code to toggle a GPIO

    Since 50MHz is the max ADCCLK and 75ns is the min S+H time, the time won't be any shorter than this (you can set the interrupt mode to early or trigger from an earlier EOC than EOC3, but the conversions will still take the same amount of time).