• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 82 subscribers
  • Views 302 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Why does a simple SRAM write take 16 accesses?

Traian Mitrache
Prodigy 180 points

We doing simple ADC acquisitions, and we have this piece of code to write the data from the ADR result to external SRAM:

 

GpioDataRegs.GPFCLR.bit.GPIOF14= 1;    // clear gpioF14 (signal LO)     DEBUG

adcConvRslts.adcA1[adcConversionCount] = AdcRegs.RESULT2  >> 4;

GpioDataRegs.GPFSET.bit.GPIOF14= 1;    // set gpioF14 = signal HI      DEBUG

The purpose of the GPIO is to help us try to figure out how long does it take to do this access. To our astonishment when we monitor the SRAM CS pin, we see 16 accesses (CS goes down 16 times).

Why does one simple write take 16 SRAM access? We tried removing the shift operation, but nothing changed.

 

  • 0
    Expert 2860 points

    Maybe C2000 access external RAM in bursts. When you verify it you should collect data into burst and then write them to external RAM.
    If it is burst related addressing RAM may require aligned access.

    Did you verify what are opcodes generated by compiler from above C code?

    Regards
    Piotr Romaniuk, Ph.D.
    ELESOFTROM

    PS
    I assume that in first line should be zero at the end: GpioDataRegs.GPFCLR.bit.GPIOF14= 1;