TMS320F28379D: CLA

Ganeshapandi K said:

My program showed warning to create CLAMathTable untill i add "F2837xRevB_c1bootROM_CLADataROMSymbols_fpu32.lib"  with first priority. After adding, my warnings vanished and still CLAsin() function is not working in my cla task.

Ganeshapandi,  

Please provide more information on how it is failing.  Is it resulting in the wrong value? Returning 0? Task not running?  

Ganeshapandi K said:

I am using Control card so i am using RAM in my cmd. Should I modify my cmd file? 

Compare with the CLA examples in the latest C2000Ware release:

• C:\ti\c2000\C2000Ware_<version>\libraries\math\CLAmath\c28\examples

Ganeshapandi K said:

2. Even though I am using CLA library, Should I also include CLA assembly source file into my project?

You don't have to include both. 

Ganeshapandi K said:

3. When I add "CLAsin.asm" source file, it atomatically shows error to add "CLAeabi.asm" but I am working in COFF output format. Help on that

What is the exact error? (provide a screenshot)

I would suggest moving to EABI at some point.  Moving forward most enhancements and improvements to the compiler will be available in EABI only.  It already has some advantages over COFF. 

You may find the CLA SW development guide useful:

https://software-dl.ti.com/C2000/docs/cla_software_dev_guide/intro.html

Regards

Lori 

1. Which of the following library files should be used for using CLAsin() function? If all should be used, then why it is so?

• "cla1_math_library_fpu32.lib" 
• "cla1_math_library_datarom_fpu32.lib"
• "F2837xRevB_c1bootROM_CLADataROMSymbols_fpu32.lib"

2. I included CLAmath header file and added the following symbols in properties 

• CLA_C
• CLA_MATH_TABLES_IN_ROM=1

3. I debugged my program initially the compiler showed the following warning 

4. Hence I made the Priority of  "F2837xRevB_c1bootROM_CLADataROMSymbols_fpu32.lib" to first in the properties window then my warning was disappeared and debugged successfully.

5. But CLAsin() operation not working. When I single step the CLAtask lines the following message comes when compiler single steps the line "CLAsin(samples)" present in CLAtask.

interrupt void Cla1Task1(void)
{
__mdebugstop();
GpioDataRegs.GPADAT.bit.GPIO26 = 1;
Result = CLAsin(samples);                       // When compiler executes this line, the message in the below figure comes
}

6. I additionally add my cmd file below

// The user must define CLA_C in the project linker settings if using the
// CLA C compiler
// Project Properties -> C2000 Linker -> Advanced Options -> Command File
// Preprocessing -> --define

#ifdef CLA_C
// Define a size for the CLA scratchpad area that will be used
// by the CLA compiler for local symbols and temps
// Also force references to the special symbols that mark the
// scratchpad are.
CLA_SCRATCHPAD_SIZE = 0x100;
--undef_sym=__cla_scratchpad_end
--undef_sym=__cla_scratchpad_start
#endif //CLA_C

--define=CLA_MATH_TABLES_IN_ROM=1

_CLAsinTable = 0xFd0a;

MEMORY
{
PAGE 0 :
   /* BEGIN is used for the "boot to SARAM" bootloader mode   */

   BEGIN           	: origin = 0x000000,   	length = 0x000002
   RAMM0           	: origin = 0x000123,   	length = 0x0002DD
   RAMD0           	: origin = 0x00B000,   	length = 0x000800
   RAMD1            : origin = 0x00B800,   	length = 0x000800
/* RAMLS4      	    : origin = 0x00A000, 	length = 0x000800 */
/* RAMLS5           : origin = 0x00A800, 	length = 0x000800 */
   RAMLS4_5         : origin = 0x00A000,   	length = 0x000800
   RAMLS1_4_5		: origin = 0x00A800, 	length = 0x000800
   RESET           	: origin = 0x3FFFC0,   	length = 0x000002

PAGE 1 :

   BOOT_RSVD        : origin = 0x000002, 	length = 0x000121     /* Part of M0, BOOT rom will use this for stack */
   RAMM1            : origin = 0x000400, 	length = 0x0003F8     /* on-chip RAM block M1 */
// RAMM1_RSVD       : origin = 0x0007F8, 	length = 0x000008     /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
/* RAMLS0          	: origin = 0x008000,   	length = 0x000800*/

   EPWM1ISR_LS0		: origin = 0x008000,	length = 0x000050
   ECAP1ISR_LS0		: origin = 0x008050,	length = 0x000050

   RAMLS0          	: origin = 0x080A0,   length = 0x000760

   RAMLS1          	: origin = 0x008800,   length = 0x000800
   RAMLS2      		: origin = 0x009000,   length = 0x000800
   RAMLS3      		: origin = 0x009800,   length = 0x000800

   RAMGS0           : origin = 0x00C000,   length = 0x001000
   RAMGS1           : origin = 0x00D000,   length = 0x001000
   RAMGS2           : origin = 0x00E000,   length = 0x001000
   RAMGS3           : origin = 0x00F000,   length = 0x001000
   RAMGS4           : origin = 0x010000,   length = 0x001000
   RAMGS5           : origin = 0x011000,   length = 0x001000
   RAMGS6           : origin = 0x012000,   length = 0x001000
   RAMGS7           : origin = 0x013000,   length = 0x001000
   RAMGS8           : origin = 0x014000,   length = 0x001000
   RAMGS9           : origin = 0x015000,   length = 0x001000
   RAMGS10          : origin = 0x016000,   length = 0x001000

// RAMGS11     : origin = 0x017000, length = 0x000FF8   		/* Uncomment for F28374D, F28376D devices */

// RAMGS11_RSVD : origin = 0x017FF8, length = 0x000008    		/* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

   RAMGS11          : origin = 0x017000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
   RAMGS12          : origin = 0x018000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
   RAMGS13          : origin = 0x019000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
   RAMGS14          : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
   RAMGS15          : origin = 0x01B000, length = 0x000FF8     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */

//   RAMGS15_RSVD : origin = 0x01BFF8, length = 0x000008    /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
                                                            /* Only on F28379D, F28377D, F28375D devices. Remove line on other devices. */

   EMIF1_CS0n       : origin = 0x80000000, length = 0x10000000
   EMIF1_CS2n       : origin = 0x00100000, length = 0x00200000
   EMIF1_CS3n       : origin = 0x00300000, length = 0x00080000
   EMIF1_CS4n       : origin = 0x00380000, length = 0x00060000
   EMIF2_CS0n       : origin = 0x90000000, length = 0x10000000
   EMIF2_CS2n       : origin = 0x00002000, length = 0x00001000

   CANA_MSG_RAM     : origin = 0x049000,   length = 0x000800
   CANB_MSG_RAM     : origin = 0x04B000,   length = 0x000800

   CLA1_MSGRAMLOW   : origin = 0x001480,   length = 0x000080
   CLA1_MSGRAMHIGH  : origin = 0x001500,   length = 0x000080

   CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
   CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400
}

SECTIONS
{
   codestart        : > BEGIN,      PAGE = 0
   .text            : >> RAMD0 | RAMD1 | RAMLS4_5,    PAGE = 0
   .cinit           : > RAMM0,      PAGE = 0
   .switch          : > RAMM0,      PAGE = 0
   .reset           : > RESET,      PAGE = 0, TYPE = DSECT /* not used, */
   .stack           : > RAMM1,      PAGE = 1

#if defined(__TI_EABI__)
   .bss             : > RAMLS2,    PAGE = 1
   .bss:output      : > RAMLS2,    PAGE = 1
   .init_array      : > RAMM0,     PAGE = 0
   .const           : > RAMLS3,    PAGE = 1
   .data            : > RAMLS3,    PAGE = 1
   .sysmem          : > RAMLS3,    PAGE = 1
#else
   .pinit           : > RAMM0,     PAGE = 0
   .ebss            : > RAMLS2,    PAGE = 1
   .econst          : > RAMLS3,    PAGE = 1
   .esysmem         : > RAMLS3,    PAGE = 1
#endif

#if !(CLA_MATH_TABLES_IN_ROM)
   CLA1mathTables    : > RAMLS1_4_5,              PAGE = 0
#endif

   Filter_RegsFile  : > RAMGS0,	    PAGE = 1

   .em1_cs0         : > EMIF1_CS0n, PAGE = 1
   .em1_cs2         : > EMIF1_CS2n, PAGE = 1
   .em1_cs3         : > EMIF1_CS3n, PAGE = 1
   .em1_cs4         : > EMIF1_CS4n, PAGE = 1
   .em2_cs0         : > EMIF2_CS0n, PAGE = 1
   .em2_cs2         : > EMIF2_CS2n, PAGE = 1

    /* CLA specific sections */
   Cla1Prog         : > RAMLS4_5, PAGE=0

   CLADataLS0		: > RAMLS0, PAGE=1
   CLADataLS1		: > RAMLS1, PAGE=1

   EPWM_INT_ISR 	: > EPWM1ISR_LS0, PAGE = 1
   ECAP1_ISR		: > ECAP1ISR_LS0, PAGE = 1
   CPU2toCPU1_IPC1 	: > RAMLS3, PAGE = 1


   Cla1ToCpuMsgRAM  : > CLA1_MSGRAMLOW,   PAGE = 1
   CpuToCla1MsgRAM  : > CLA1_MSGRAMHIGH,  PAGE = 1

   /* The following section definition are for SDFM examples */
   Filter1_RegsFile : > RAMGS1,	PAGE = 1, fill=0x1111
   Filter2_RegsFile : > RAMGS2,	PAGE = 1, fill=0x2222
   Filter3_RegsFile : > RAMGS3,	PAGE = 1, fill=0x3333
   Filter4_RegsFile : > RAMGS4,	PAGE = 1, fill=0x4444

#ifdef __TI_COMPILER_VERSION__
   #if __TI_COMPILER_VERSION__ >= 15009000
    .TI.ramfunc : {} > RAMM0,      PAGE = 0
   #else
    ramfuncs    : > RAMM0      PAGE = 0   
   #endif
#endif

#ifdef CLA_C
   /* CLA C compiler sections */
   //
   // Must be allocated to memory the CLA has write access to
   //
   CLAscratch       :
                     { *.obj(CLAscratch)
                     . += CLA_SCRATCHPAD_SIZE;
                     *.obj(CLAscratch_end) } >  RAMLS1,  PAGE = 1

   .scratchpad      : > RAMLS1,       PAGE = 1
   .bss_cla		    : > RAMLS1,       PAGE = 1
   .const_cla	    : > RAMLS1,       PAGE = 1
#endif //CLA_C

    GROUP : > CPU1TOCPU2RAM, PAGE = 1
    {
        PUTBUFFER
        PUTWRITEIDX
        GETREADIDX
    }

    GROUP : > CPU2TOCPU1RAM, PAGE = 1
    {
        GETBUFFER :    TYPE = DSECT
        GETWRITEIDX :  TYPE = DSECT
        PUTREADIDX :   TYPE = DSECT
    }


}

7. I also attach my CLA initialization

void Init_CLA()
{
    asm(" EALLOW");                                                             // Enable EALLOW protected register access
/*
    DevCfgRegs.DC1.bit.CPU1_CLA1 = 1;                                           // Enable CPU1.CLA1

    //---------------------------------- Initialize and wait for CLA1ToCPUMsgRAM

    MemCfgRegs.MSGxINIT.bit.INIT_CLA1TOCPU = 1;
    while(MemCfgRegs.MSGxINITDONE.bit.INITDONE_CLA1TOCPU != 1){};

    //---------------------------------- Initialize and wait for CPUToCLA1MsgRAM

    MemCfgRegs.MSGxINIT.bit.INIT_CPUTOCLA1 = 1;
    while(MemCfgRegs.MSGxINITDONE.bit.INITDONE_CPUTOCLA1 != 1){};

*/


    //--------------------------------------------------------- Enable CPU1.CLA1

    DevCfgRegs.DC1.bit.CPU1_CLA1 = 1;

    //--------------------------------------------------------- Enable CPU2.CLA1

    DevCfgRegs.DC1.bit.CPU2_CLA1 = 1;


    //------------------------------------------------ Master CPU and CLA Select

    MemCfgRegs.LSxMSEL.bit.MSEL_LS0 = 1;                                        // 0=CPU    1=CPU and CLA
    MemCfgRegs.LSxMSEL.bit.MSEL_LS1 = 1;                                        // 0=CPU    1=CPU and CLA
    MemCfgRegs.LSxMSEL.bit.MSEL_LS2 = 0;                                        // 0=CPU    1=CPU and CLA
    MemCfgRegs.LSxMSEL.bit.MSEL_LS3 = 0;                                        // 0=CPU    1=CPU and CLA
    MemCfgRegs.LSxMSEL.bit.MSEL_LS4 = 1;                                        // 0=CPU    1=CPU and CLA
    MemCfgRegs.LSxMSEL.bit.MSEL_LS5 = 1;                                        // 0=CPU    1=CPU and CLA

    //---------------------------- CLA Data Memory and CLA Program Memory Select

    MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS0 = 0;                                    // 0=CLA data memory    1=CLA program memory
    MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS1 = 0;                                    // 0=CLA data memory    1=CLA program memory
    MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS2 = 0;                                    // 0=CLA data memory    1=CLA program memory
    MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS3 = 0;                                    // 0=CLA data memory    1=CLA program memory
    MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS4 = 1;                                    // 0=CLA data memory    1=CLA program memory
    MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS5 = 1;                                    // 0=CLA data memory    1=CLA program memory

    //------------------------------------ Initialize CLA task interrupt vectors

    Cla1Regs.MVECT1 = (uint16_t)(&Cla1Task1);

    //--------------------------------------------- Select Task interrupt source

    DmaClaSrcSelRegs.CLA1TASKSRCSEL1.bit.TASK1 = 0;                             // 0=none/sof   8=ADCBINT3  16=ADCDINT1  32=XINT4     42=EPWM7INT   70=TINT2     78=ECAP4INT   95=SD1INT     114=SPIRXINTC
                                                                                // 1=ADCAINT1   9=ADCBINT4  17=ADCDINT2  33=XINT5     43=EPWM8INT   71=MXEVTA    79=ECAP5INT   96=SD2INT
                                                                                // 2=ADCAINT2  10=ADCBEVT   18=ADCDINT3  36=EPWM1INT  44=EPWM9INT   72=MREVTA    80=ECAP6INT  107=UPP1INT
                                                                                // 3=ADCAINT3  11=ADCCINT1  19=ADCDINT4  37=EPWM2INT  45=EPWM10INT  73=MXEVTB    83=EQEP1INT  109=SPITXINTA
                                                                                // 4=ADCAINT4  12=ADCCINT2  20=ADCDEVT   38=EPWM3INT  46=EPWM11INT  74=MREVTB    84=EQEP2INT  110=SPIRXINTA
                                                                                // 5=ADCAEVT   13=ADCCINT3  29=XINT1     39=EPWM4INT  47=EPWM12INT  75=ECAP1INT  85=EQEP3INT  111=SPITXINTB
                                                                                // 6=ADCBINT1  14=ADCCINT4  30=XINT2     40=EPWM5INT  48=TINT0      76=ECAP2INT  87=HRCAP1INT 112=SPIRXINTB
                                                                                // 7=ADCBINT2  15=ADCCEVT   31=XINT3     41=EPWM6INT  69=TINT1      77=ECAP3INT  88=HRCAP2INT 113=SPITXINTC

    //------------------------------------ CLA1TASKSRCSELx register lock control

    DmaClaSrcSelRegs.CLA1TASKSRCSELLOCK.bit.CLA1TASKSRCSEL1 = 0;                // Write a 1 to lock (cannot be cleared once set)
    DmaClaSrcSelRegs.CLA1TASKSRCSELLOCK.bit.CLA1TASKSRCSEL2 = 0;                // Write a 1 to lock (cannot be cleared once set)


    asm(" EDIS");                                                               // Disable EALLOW protected register access

}

Ganeshapandi K said:

1. Which of the following library files should be used for using CLAsin() function? If all should be used, then why it is so?

1. "cla1_math_library_fpu32.lib" 
2. "cla1_math_library_datarom_fpu32.lib"
3. "F2837xRevB_c1bootROM_CLADataROMSymbols_fpu32.lib"

If you want to use the lookup tables provided in the ROM then include (2) and (3).  Note: This is how the sin example I mentioned is setup as provided.  library (1) is excluded from the build.   

(1) and (2) is the CLA code itself. Use one or the other depending if you are using the tables in ROM or want to have the tables in RAM. 

(3) tells the linker where the tables are located in ROM when using (2) (refer to page 13/14 of the CLA math guide).

Ganeshapandi K said:

5. But CLAsin() operation not working. When I single step the CLAtask lines the following message comes when compiler single steps the line "CLAsin(samples)" present in CLAtask.

Code Composer Studio is only asking you where the source is to the library so that it can show you the source code as you step through it.  Unfortunately it doesn't know where it is on your system - only where it was when we built the library.  (an annoying issue we have been looking to resolve).    Click on "locate file" and browse to the source code directory.  CCS will then be able to display the source while single stepping the code. 

I don't see anything obvious in the init or .cmd file glancing over them.  You can compare these to the working example and see if you spot anything.  Stepping through the sin function will hopefully point to a cause. 

Regards

Lori

I had a couple of typos in the previous post when describing the libraries in question 1 - I've corrected them. 

Thank you so so much Lori

1. Here, What is meant by look up table? does it mean prebuilt sine input values or they are just address locations of trigonometry functions (as mentioned in      TRM) ?

2. Give me correction If I am wrong,

• When compiler sees "CLAsin()" function, it transfers the control to the look up table present in the ROM.
• Compiler can find The location of "CLAsin()" only when I mention the location in cmd file as below or I should include "cla1_math_library_datarom_fpu32.lib"  and "F2837xRevB_c1bootROM_CLADataROMSymbols_fpu32.lib" in properties

_CLAsinTable = 0xFd0a;    // For CLAsin()

MEMORY
{
PAGE 0 :..........

PAGE 1 :.........
}
SECTIONS
{
}

3. If above thoughts are right, then a question arises that "Is ROM having the stored inbuilt program for trigonometry functions?" and If I don't use this Look up table facility then How does the compiler react when it sees CLAsin() ? (note: but included "cla1_math_library_fpu32.lib" )

Thank you so much Lori for your detail explanation for my previous post.

Ganeshapandi K said:

1. Here, What is meant by look up table? does it mean prebuilt sine input values or they are just address locations of trigonometry functions (as mentioned in      TRM) ?

You can examine the lookup tables in the IQMath library source code.  The files with the word "Table" in the title are lookup tables.  They are also described in the source code file comments for the particular function.

Ganeshapandi K said:

When compiler sees "CLAsin()" function, it transfers the control to the look up table present in the ROM.

Refer to the comments in the source code for the CLA sin function.  The comments indicate when the table value is being read.

Ganeshapandi K said:

Compiler can find The location of "CLAsin()" only when I mention the location in cmd file as below or I should include "cla1_math_library_datarom_fpu32.lib"  and "F2837xRevB_c1bootROM_CLADataROMSymbols_fpu32.lib" in properties

The file "F2837xRevB_c1bootROM_CLADataROMSymbols_fpu32.lib" has pointers (addresses) to the tables in the ROM.  This saves RAM memory for other things.  

Please refer to the examples.  There are examples for tables in ROM and tables not in ROM.  Select the option by right clicking on the project -> build configurations -> set active -> <your choice>

Ganeshapandi K said:

3. If above thoughts are right, then a question arises that "Is ROM having the stored inbuilt program for trigonometry functions?" and If I don't use this Look up table facility then How does the compiler react when it sees CLAsin() ? (note: but included "cla1_math_library_fpu32.lib" )

The compiler will tell you that the table is an unresolved symbol.  

Regards

Lori