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TMS320F28377D: RAM access time

May
Genius 9880 points

Part Number: TMS320F28377D

Hi Team, 

Good day, do we have information  about the RAM access time for CPU and CLA  of TMS320F28377D device? 

Thank you and looking forward for your kind response.

Regards,

Maynard.

  • 0
    TI__Guru* 83740 points

    Maynard,

    I'm 99% certain that all internal RAMs accessed by the CPU, CLA, or DMA are all at 0 WaitStates up to the max CPU frequency of 200MHz. 

    There would be some exceptions if the individual RAM blocks were attempted to be accessed by the CPU and either the CLA or DMA at the same time, but this can be avoided by allocating the RAM accordingly, for instance if the CPU and CLA were trying to access RAM L0 at the same time, there would be arbitration and one would get stalled.

    I will get a definitive/final answer no later than tomorrow end of day.

    Best,

    Matthew

  • 0 in reply to MatthewPate
    TI__Guru* 83740 points

    Maynard,

    Just writing back to confirm that my above statement is accurate, all RAM is 0WS.  Let us know if you have further questions.

    Best,

    Matthew 

  • 0 in reply to MatthewPate
    TI__Genius 9880 points

    Hi Matthew ,

    I just received reply from customer and there some follow-up questions. For me to not miss any information, I will copy query below.

    "Thanks for your answer, the case where both CLA and CPU access the RAM at the same time is precisely the one I want to dig a little. what is the maximum access time including arbitration/round robin time ? I read about a document "Detailed Safety Analysis Report (SAR)", I'd like to retrieve it, what is the procedure ? do I need an NDA ?"

    Regards,

    Maynard

  • 0 in reply to May
    TI__Guru* 83740 points

    Maynard,

    I would ask the customer to look at the memory arbitration section in the TRM .  This details the arbitration, blocks, and priority flags that are available for each memory type.

    At a high level if a memory is configured as CLA Program, then any CPU access(except for debug accesses) will be blocked.  Only when a block is configured as CLA data will the arbitration apply. 

    I will check on how to get the report on safety the customer has mentioned and get back with you.

    Best,

    Matthew

  • 0 in reply to MatthewPate
    TI__Guru* 83740 points

    Maynard,

    I am still waiting on an exact answer from another colleague, but I believe that this document should contain all our Safety collateral, either links to download or links to request where needed.  Let me know if this get the customer what they need.

    Best,
    Matthew

  • 0 in reply to MatthewPate
    TI__Genius 9880 points

    Hi Matthew,

    Thank you for the information. I just received response from customer that they did not find any measure on worst case RAM time access in the document provided. 

    Regards,

    Maynard

  • 0 in reply to May
    TI__Guru* 83740 points

    Maynard,

    Based on my reading of the TRM/DS in this regard if there are multiple accesses to the same block of RAM each will be treated in a round robin type scheme.  So, if the CLA and CPU are both trying to access RAM L0, for example, then the CPU would get a single access, then the arbitration would let the CLA get a single access, and so forth until either is done.

    If this were to continue, we could say that the RAM L0 would be WS = 1 for both the CPU and CLA in this case.  Certainly this wouldn't continue perpetually though, and would likely only occur if the CPU/CLA were processing the same data.  I think this would be more likely to occur in the CPU/CLA message RAMs.

    Keep in mind that each physical RAM block can be accessed independently; so if CLA is accessing RAM L0 the CPU could be accessing RAM L1 without conflict.

    Let me know if this clears things up.

    Best,

    Matthew  

  • 0 in reply to MatthewPate
    Prodigy 50 points

    Many Thanks for your answer it definitely clears things up, I can now theoretically quantify the delay induced by simultaneous CPU/CLA access.

    Can you confirm it's the same logic for Global shared RAM ?

    meaning that :

    - there's a 0 cycle access time for single access.

    - worst case is 3 cycles delay in case of simultaneous access by CPU1/CPU2/DMA1/DMA2.

    regards,

    Sylvain

  • 0 in reply to bessiere sylvain
    TI__Genius 17041 points

    Hi Sylvain, please note Matthew is out of the office due to the US holiday, you can expect to hear back by Tuesday or Wednesday next week.

    Regards,

    Joe

  • 0 in reply to bessiere sylvain
    TI__Guru* 83740 points

    Sylvain,

    This is correct, in the case of all 4 simultaneous access to a global shared RAM, 1 of the requests will see the max of 3 cycles delay until it gets its first access.

    Best,

    Matthew

  • 0 in reply to MatthewPate
    Prodigy 50 points

    ok thanks, that's clear, I have my answer.

    best regards,

    Sylvain