Configuration of the ADC clock on 28069?

Hello Filipe.

SysCtrlRegs.LOSPCP.all = 0x0002; set the clock of SPI(A/B) and SCI(A/B) to run at 80MHz/4 = 20MHz.

SysCtrlRegs.XCLK.bit.XCLKOUTDIV=2; set the clock of ADC to 80MHz/2 = 40MHz.

The maximum adc clock is 40MHz. The adc requires 13 clock cycles to convert = 325ns.

See SPRS698A–NOVEMBER 2010–REVISED JANUARY 2011 page 46/48.

Hello Mauro,

Thanks for your reply, but to configure the ADC, the registers are not the one you said.

In the F28069 you have registers:

EALLOW;

    AdcRegs.ADCCTL2.bit.CLKDIV2EN = 1;

    AdcRegs.ADCCTL2.bit.CLKDIV4EN = 1;

EDIS;

If you look in the file SPRS698A–NOVEMBER 2010–REVISED JANUARY 2011 page 46/48, you can see that the divider you mention is not used in the ADC module. The ADC module is supplied with the SYSCLKOUT.

Best regards,

Filipe Teixeira

Filipe,

register LOSPCP is not related to the ADC.  To setup the ADC of the 28069 to run at 40 MHz, all you have to do is to set AdcRegs.ADCCTRL2.bit.CLKDIV2EN = 1. This command will half the frequency of SYSCLKOUT. Please inspect function "InitAdc()" in file "F2806x_ADC.c", which can be found in Controlsuite / device_support.

Thanks for the reply.

You can see from my previous post, that I already use that register. There is also the register CLKDIV4EN that allows to divide the clock by 4.

In the example "InitAdc()" you said, I think there is an error. The register CLKDI2EN is EALLOW protected, and in the example the access is not using the EALLOW macro, so it will not configure the clock correctly (the ADC will be using the 80MHz clock)...

Best Regards,

Filipe Teixeira