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TMS320F280025C: ePWM Digital Compare Control register (DCxCTL) does not contains latch and clear options as shown in block diagram

Aditya Padmanabha
Expert 1440 points
Part Number: TMS320F280025C

Hi,

I am trying to use F280025C Control Card, ePWM Digital Control module. In the block diagram it is shown that there are options present in DCxCTL register to latch (EVTyLATSEL]) or clear (EVTyLATclrSEL])  the Digital compare event (DCxEVTy). But I do not see the same options in the register description as shown below. Can you let us know about this and how to make use of it?

Thanks,

Aditya

  • 0
    TI__Guru 52040 points

    This will be fixed in the next revision.

    For now, here is the register descriptions:

    0 EVT1SRCSEL DCAEVT1 Source Signal 0 R/W SYSRSn DCAEVT1 Source Signal Select

     0: Source Is DCAEVT1 Signal
     1: Source Is DCEVTFILT Signal
    1 EVT1FRCSYNCSEL DCAEVT1 Force Sync Signal 0 R/W SYSRSn DCAEVT1 Force Synchronization Signal Select

    0: Source is synchronized with EPWMCLK
    1: Source is passed through asynchronously
    2 EVT1SOCE DCAEVT1 SOC Enable 0 R/W SYSRSn DCAEVT1 SOC, Enable/Disable

     0: SOC Generation Disabled
     1: SOC Generation Enabled
    3 EVT1SYNCE DCAEVT1 SYNC Enable 0 R/W SYSRSn DCAEVT1 SYNC, Enable/Disable

     0: SYNC Generation Disabled
     1: SYNC Generation Enabled
    4 EVT1LATSEL DCAEVT1 Latched signal select 0 R/W SYSRSn DCAEVT1 Latched signal select:
    0 Does not select the DCAEVT1 latched signal (Refer figure “Modifications to DCAEVT1.force/DCAEVT2.force generation.”)  as source of DCAEVT1.force.
    1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force.
    6..5 EVT1LATCLRSEL DCAEVT1 Latched clear source select 0 R/W SYSRSn DCAEVT1 Latched clear source select:
    00 CNT_ZERO event clears DCAEVT1 latch.
    01 PRD_EQ event clears DCAEVT1 latch.
    10          CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch.
    11          Reserved.
    7 EVT1LAT Indicates the status of DCAEVT1LAT signal. 0 R SYSRSn Indicates the status of DCAEVT1LAT signal.
      0  The DCAEVT1LAT latch is cleared.
      1  The DCAEVT1LAT latch is set.
    8 EVT2SRCSEL DCAEVT2 Source Signal 0 R/W SYSRSn DCAEVT2 Source Signal Select

     0: Source Is DCAEVT2 Signal
     1: Source Is DCEVTFILT Signal
    9 EVT2FRCSYNCSEL DCAEVT2 Force Sync Signal 0 R/W SYSRSn DCAEVT2 Force Synchronization Signal Select

    0: Source is passed through asynchronously
    1: Source is synchronized with EPWMCLK
    11..10 Reserved Reserved 0 R=0 SYSRSn
    12 EVT2LATSEL DCAEVT2 Latched signal select 0 R/W SYSRSn DCAEVT2 Latched signal select:
    0 Does not select the DCAEVT2 latched signal (Refer figure “Modifications to DCAEVT1.force/DCAEVT2.force generation.”)     as source of DCAEVT2.force.
    1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force.
    14..13 EVT2LATCLRSEL DCAEVT2 Latched clear source select 0 R/W SYSRSn DCAEVT2 Latched clear source select:
    00 CNT_ZERO event clears DCAEVT2 latch.
    01 PRD_EQ event clears DCAEVT2 latch.
    10          CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch.
    11          Reserved.
    15 EVT2LAT Indicates the status of DCAEVT2LAT signal. 0 R SYSRSn Indicates the status of DCAEVT2LAT signal.
      0  The DCAEVT2LAT latch is cleared.
      1  The DCAEVT2LAT latch is set.