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TMS320F28388D: Possible mistake in the TRM CM Clocking System diagram

jimj2713
Expert 2405 points

Part Number: TMS320F28388D

These diagrams are immensely helpful. I am debugging an MCAN implementation, so I am going through all of the clocking. At the bottom-right of figure 41-1 CM Clocking System, I think(?) there are 2 issues:

1. The MCANBCLKSEL register should be the MCANABITCLKSEL register?

2. Also the 3 inputs to that same multiplexer are AUXCLKIN, CM.PERx.SYSCLK, and AUXPLLRAWCLK. If I am correct about issue 1 above, these 3 inputs should be AUXCLKIN, CPU1/CPU2/CM.PERx.SYSCLK, and AUXPLLRAWCLK, because that is what is stated in the MCANABITCLKSEL register description on page 219.

If I am incorrect about this, please let me know, as I am probably configuring my MCANA clock wrong.

Thanks,

Jim

  • 0
    TI__Guru** 117431 points

    Hi Jim,

     1. The MCANBCLKSEL register should be the MCANABITCLKSEL register?

    Yes, you are right.

     2. Also the 3 inputs to that same multiplexer are AUXCLKIN, CM.PERx.SYSCLK, and AUXPLLRAWCLK. If I am correct about issue 1 above, these 3 inputs should be AUXCLKIN, CPU1/CPU2/CM.PERx.SYSCLK, and AUXPLLRAWCLK, because that is what is stated in the MCANABITCLKSEL register description on page 219.

    This is correct because currently MCAN access from CPU1 is not supported. We are evaluating this feature and will update this in next revision of document if decided to support it.

    Regards,

    Vivek Singh