TMS320F280049: FCL: eQEP Unit Timer Synchronization w/ ADC SOC

The QEP and PWM clocks are disabled during initializing time, and after both these peripheral registers are appropriately set, then the clocks are enabled. This will sync both peripherals to one cycle delay at best.

Thanks Ramesh,

I just did a bit of a dive trying to see where that is happening. Just to clarify, I am using the dual_axis_servo_drive_fcl_qep_f28004x in the MotorControl SDK v3.00.01.00 repository.

I see the fact that all the system clocks are enabled by Device_Init(). The PWM timebase clock is then disabled in HAL_setupMotorPWMs for each motor.  And I see that it isn't getting re-enabled until after the HAL_setMotorParams completes for each motor. Line 250 of dual_axis_servo_drive.c

    // set the driver parameters for motor 1
    HAL_setMotorParams(halMtrHandle[MTR_1]);

    // set the driver parameters for motor 2
    HAL_setMotorParams(halMtrHandle[MTR_2]);

    // PWM Clocks Enable
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);

However, I don't understand is where the QEP clocks are getting tied to the same clock.  Or where the phase shift for the motor 2 eQEP UTO occurs.  It kinda looks like the eQep 1 UTO is started, then a while later eQep 2 UTO is started, then a while later TBCLKSYNC is started with a defined offset between the two PWM sets.  But the time gap between eQEP UTO and Motor timebases are a bit random.

What am I missing? Thanks!

-Colin

It skipped my attention, will pass it over to my colleague to respond to this, as it was ported over from an earlier project.

Thanks,

Am I correct in interpreting that the eQEP UTO capture time is not synchronized with the ADC in the dual motor example beyond running at the same frequency (10 Khz)?  Thats fine if so.  And I see ways to align it, but I just wanted to verify that there isn't another mechanism that is already implemented that I am missing.

Thanks,

-Colin