• State TI Thinks Resolved
  • Locked Locked
  • Replies 4 replies
  • Answers 1 answer
  • Subscribers 83 subscribers
  • Views 483 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F28075: F28075 POR question

Huihuang Chen
Expert 4060 points
Part Number: TMS320F28075


Hi Champ,

From the datasheet it is seems POR just on VDDIO,  VDD without POR , may I know my understanding is correct or not?

Suppose the external RC value is : Pull up resistor is 2.2 kΩ and the capacitance is 100 nF, another question is when the VDDIO over the POR threshold, how long the XRS pin will go to high ? if the VDDIO lower than the POR threshold, how long time the XRS pin will go to low?

  • 0
    TI__Guru* 81560 points

    Huihuang,

    Thanks for reaching out to the E2E forum with your question.

    According to figure 5-5 in the F28075 datasheet, the XRSn pin will be held low by the device for ~100us after both the VDDIO(3.3V) and VDD(1.2V) are within tolerance.  After this time the drive low will be released and your external RC circuit will take over the time constant to let the pin ramp to inactive high.

    I believe that the internal supervisor will trip if either voltage goes out of range from spec.

    Best,

    Matthew

  • 0 in reply to MatthewPate
    TI__Expert 4060 points

    Hi Matthew,

    So did you means the POR be on VDD and VDDIO both, if so, could you advise the POR threshold for VDD?

    you explained the time delay from VDDIO raise up case ,  may i know for VDDIO drop lower than POR threshold case, how long for XRS held high ?

  • 0 in reply to Huihuang Chen
    TI__Guru* 81560 points

    Huihuang,

    I had mis-linked in the F2837xD datasheet, while the behavior is the same for the F28075 I'll correct the link to that DS after I post this update.

    I spoke with some others here at TI and there is some additional details I need to provide.

    The POR on the device does indeed monitor both the VDDIO and VDD rails, but the thresholds are well below the Vmin of the device.  The trigger points are ~2.4V for the VDDIO rail and ~1.0V for the 1.2V rail.

    The intent of this logic is to ensure that the IO pins remain glitchless during power up.  Once both these thresholds are met we will see the 100us delay before the XRSn pin is released by the device.  If your power ramp on the other supplies is such that 100us after they hit 2.4V and 1.0V they will be inside the Vmin of the device then you can rely on this to hold reset adequately.  If not, then we recommend an external SVS that will hold XRSn until the rails reach Vmin.

    For a falling VDDIO/VDD condition, this would likely ensure that the device is operating within spec until the reset is pulled active again at the 2.4V or 1.0V limits.  In this case a SVS would be needed to prevent the device from running outside its Voltage specs.

    For the F2807x device, there is an additional case where the internal VREG is used to supply the 1.2V rail.  In this case the internal VREG will be at full potential by the time the POR releases the XRSn signal, based on the VDDIO line only.  Likewise, you would only need to monitor the VDDIO for a falling event.

    Let me know if this clears things up.

    Best,

    Matthew

  • 0 in reply to MatthewPate
    TI__Expert 4060 points

    Hi Matthew,

    Very clear and thanks a lot!