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TMS320F280049C: CAN Error interrupts (CAN_ES register)

Davide Dentoni
Prodigy 175 points
Part Number: TMS320F280049C

Hello,
can anybody provide me more details about the CAN_ES register and related interrupts ?

The sentence in Technical Reference Manual is
"This register indicates error conditions, if any, of the CAN module. Interrupts are generated by PER, BOff
and EWarn bits (if EIE bit in CAN Control Register is set) and by RxOk, TxOk, and LEC bits (if SIE bit in
CAN Control Register is set)."

Does it mean that an interrupt is generated on any change (0 to 1 and 1 to 0) of EWarn, BOff, PER ?

Let's take the following example:
enabled CAN_INT_IE0 and CAN_INT_ERROR (not CAN_INT_STATUS).

When an internal Error counter overcomes 96, I expect EWarn = 1 and an interrupt triggered.
Inside the interrupt function I read the CAN_ES register (clearing the EWarn flag).
If at next transmission or reception the counter is still bigger than 96, EWarn  will be set again to 1 and another interrupt will be triggered ?

What happens when a counter overcomes 127 ?
I guess EPass is set to 1 (but without interrupt). What about EWarn ? Is it going still to be set to 1 (since the counter is > 96) ?
Are the flags independent each other, or the most important inhibits the others (BOff inhibits EPass and EWarn) ?

Finally, it seems to me that the only way to catch the Error Active condition is to enable also CAN_INT_STATUS and check under interrupt the following condition
((RxOk = 1) or (TxOk = 1)) and ((BOff or EWarn or EPass) = 0)
Is it right or it is enough the transition 1 to 0 of EWarn to trigger an interrupt ?

Thank you in advance.

  • 0
    TI__Mastermind 37670 points

    Hi Davide,

    As long as SIE and/or EIE bits in the CAN_CTL register are set, the corresponding error (PER, BOff, EWarn) and status (RxOk, TxOk, LEC) flags will generate an interrupt.  Interrupt is only generated when a flag state changes from 0 to 1 (emphasis on the condition that SIE/EIE bits are set, otherwise these are only flags).

    As long as EWarn value is greater than 96, the EWarn flag would always be set to 1, and if EIE is set, an interrupt will be generated, and to avoid the risk of overflow, the interrupt has to be serviced (or cause of the error identified/corrected).  The way the error counters increment/decrement is a bit complex, where a transmitting node is assigned 8 counts and a receiving node is assigned 1 count, for instance, that I am aware of (there might be some other criteria that affects the error counter that I do not know of).  A successful transaction would decrement the error counters with the corresponding counts depending whether node is transmitting (-8) or receiving (-1) and will not do anything if the counters are at 0, while a failed transaction will increase the counters accordingly.

    What happens if the error counter goes over 127? Yes, EPass (error passive) is set to 1 as well as EWarn. They are independent bits.   If this is a transmitting node, it will transmit an error passive frame which does not destroy other bus traffic.  It will keep sending this until the transmit error counter reaches 255 and if it does, the transmitting node will enter bus-off state and disconnects itself from the network, making the EPass/EWarn flag information practically useless.  There is a feature in the F280049C device that will automatically attempt to turn the bus on (ABO bit in CAN_CTL).  If ABO bit is set, the module will attempt a bus-off recovery sequence (details available in TRM) and clear the error counters in the process.

    Active error is generated by the transmitter when the transmit error count is less than 127 and transmission is not successful.  I believe the transmitting node will also send an active error frame consisting of 6 dominant bit, so unless you are observing the traffic through an oscilloscope on the bus to capture this frame, one of the ways to detect this is by inspecting the CAN_ES register and looking to see if TxOk bit remained cleared (0) after data is sent by the CAN module.

    Regards,

    Joseph

  • 0 in reply to Joseph Casuga
    Prodigy 175 points

    Hello Joseph,

    it is a bit more clear to me, but I have a further question about the mechanism of flag setting:

    you wrote "As long as EWarn value is greater than 96, the EWarn flag would always be set to 1, and if EIE is set, an interrupt will be generated, and to avoid the risk of overflow, the interrupt has to be serviced"

    If one error counter is greater than 96, EWarn is set and an interrupt is generated.

    When I serve the EWarn interrupt, I expect that EWarn is self cleared (by CAN_ES reading) but I also believe that the counter has the same value as before, therefore still greater than 96.

    So, what is the internal mechanism ?

    EWarn flag is set again immediately ? In this case my CPU will spend lot of time in continuous interrupt servicing

    Or Ewarn is set again after next bus activity (Frame Rx or Frame Tx) and accordingly to the new value of the error counters, effect of the latest bus activity?

    I believe that your answer (whatever it is) should be applicable to the other error flags

    Thanks